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modes
CLKLATCH output from U21B clocks the
In some
the
(U13
is shown on
page
the low eight addresses from ROM Module
true, U13
latched and the lower 4 bits of UUT ROM address latched into
is
allow
Pod to receive status information from the UUT.
U13
the
A small circuit composed of U9
(OVDRV-RESET)
signal.
(REQRESET), a line that
line that comes from the Mainframe, and enable abort
ABORT,
a
a
line from
ABORT),
Main Board schematics).
the UUT. If the
REQRESET
(OVDRV-RESET) line forces the Pod to overdrive the reset of the UUT. If
line
the
to the circuit is active, either the ABORT line from the
EN-ABORT
Mainframe or
clock latch from
the
breakpoint) can be used
CLKLATCH is cleared either
reset)
or by the
output port signal
up
The bank switch lines from U4
two banks of emulation RAM. The ERAM bank switch circuitry allows the
Pod
switch cleanly between banks of RAM without causing metastable or
to
timing problems.
Two signals called force bank
(FRCBANKB) enter the bank switch circuit
FRCBANKB are output port
FRCBANKA
FRCBANKB
and
to the Pod
consequently, not available
and,
one of the banks is forced, the forced bank is available to the Pod processor,
available
but
other bank
the
is
Using force bank to
switch
problems with the UUT processor. To make
the PLZACCBNKA/-B line
cycled.
The AND/OR gate (U19) that
enters allows two different ways
is set in one mode, the next
the banks.
When SWAP-SELECT
used for swap select when
counter output)
is
This type of
mode.
first clock
and is then set and
neither bank
and U27A is
not,
bank was available to the ROM Module
BCYCLECLK- clocks pin
clock cycle,
when
swap occurs regardless of which mode
occurs.
'This
BCYCLECLK- after the first bank
This prevents metastable conditions caused by the delay between
swap.
the two flip-flops
(U27)
of the Main Board schematics). This
5
U28D creates the overdrive reset
and
The inputs to
written to or controlled by the processor,
is
U86
an
output port
on
This circuit allows three methods
line
from
Pod goes high, the overdrive reset
the
U21B
overdrive the
UUT.
to
a RESET- (from
by
REARM.
U24 allow
and
A
(FRCBANKA)
controlled
bits
both banks of ERAM are available
are true,
the ROM Modules.
to
banks
is
nonsynchronous
used to
is
switch
swap select (SWAP-SELECT) line
the
initiate
to
BCYCLECLK- that clocks U27B swaps
true
is in the
has two accesses.
swap
that
ready.
(At
available to the Pod processor. Whichever
is
is still
swapped that actually causes the bank
is
that could produce
an
Ul3
latch
When CLKLATCH goes
1.
circuit are reset request
this
shown of page
(UB6 is
of
overdriving
a comparator for a
(preset
as
Mainframe or power-
the
Pod to
the
switch
force bank
and
Ul6.
(FRCBANKA and
at
the Pod processor.) If both
by
the ROM Modules.
to
can cause runtime
and
clean swap between banks,
a
banks when
BCYCLECLK-
When SWAP-SELECT
a swap.
other mode,
SC11
Pod goes into RUNUUT
the
U27B gets swapped
when U27B is swapped
time,
On the next
available.)
of U27A, the actual swap
3
selected; it
was
indeterminate output
state.
9132A Service
latch
receives
(EN-
the
5
of
between
B
If only
is
(the sync
the
on
the
is
2-5
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