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9132A Service
the addresses
and
on,
When the Pod processor accesses
bus.
the ARAM data
U97 and
87 are
U39,
US0,
the address sent to the ARAM
These counters
U82, U63,
lines to the ARAM.
(U39, U50,
setting of ARAM enable (ARAM-EN).
U49
and
where the address stopped if the address counter stopped before
see
completion),
pulse from
to the ARAM
Al12
(when the Pod
ROM).
address RAM clock (ARAM-CLK) is received from the generic PAL (U32),
one edge of ARAM-CLK increments the address counter,
edge clocks the data into the ARAM.
The write signals
various AND and OR gates, depending
by
enable (ARAM-EN).
(ARAM-CLK) from U32 controls the write pulses and
Address RAM select (ARAM-SEL-) controls the chip enables, and the
read/write pulses control the output enables.
The Sync Module
UUT
and
connector
other lines
microprocessor-specific
is
another
U38
is an
passed through U38,
to the U44 latch.
the
sync
processor, which then determines what to do with the information.
the Pod is self testing, the SYNC line can
and U44 to appear transparent, which allows
U31
accurately read
The non-latched lines to the
Overdrive channel
(OVDRV3LO) are controlled
U4D pin
high (DRV-RST-HI) and overdrive reset low (DRV-RST-LO) lines control
the polarity of
2-10
these chips
on
passed through U94
is
used when the Pod is physically capturing ROM addresses.
are 4-bit counters (for a total of
and
U77
zero and count
preloaded
to
are
U79 are the address muxes. These ICs control the address
and
The addresses come either from the address counters
U77) or from the Pod processor address, depending on the
and
Ul4
pair of input
are a
SSO and SS1 (two sync
counter.
the sync
controlled
is
address RAM mode,
is in the
operating in the address RAM mode and
When the Pod
is
and WL-)
(WU-
If ARAM-EN is true, the address RAM clock
basically a buffer that monitors several lines
is
drives the signals up the 50-pin ribbon cable to the Sync Module
Eight of
the lines are
(J3).
microprocessor-specific status
are
lines is
always the UUT
microprocessor
input buffer
for the
high speed timing
are sent to the Personality Module connector and
they
and U44 latch
U31
pulse. These latches can
the Pod processor.
by
Sync
3
high (OVDRV3HI)
by the
line and timed
13)
by
the
reset
signal
straight through to the ARAM data
go
ARAM, ARAM-EN is off
the
U99 to
the
and
capturing ROM addresses.
Pod
is
when the
until
full.
up
that monitor the address counter
ports
state machine indicators),
ARAM-SEL-0
by
ie.,
output enable
and
mode of address RAM
on the
data (used for data capture).
control
and
always the processor clock (BCLOCK-);
reset.
lines.
condition of these
the
be read
then
as an
high, forcing the lines to
be set
all
Module connector control the overdrives.
overdrive channel
and
overdrive channel
the Personality Module. The overdrive reset
the UUT reset
sent
to
and
Pod processor
bus.
bits) that generate
12
(fo
the
and
sync
and
ARAM-SEL-1
the Pod is accessing
an
the opposite
and
are controlled
(OE-)
chip enables,
any
the
on
The
One of the
lines.
Once the lines have
end of
lines at the
the Pod
input port
by
When
the latched lines to be
low
3
(OVDRVCH3 at
3
Overdrive reset
line.
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