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Board Emulation
Main
The Main Board Emulation RAM control circuitry
Main Board schematic (Figure
The Pod processor can
emulation RAM
processor can read
bank
being used
is
(BANKAAVAIL and BANKBAVAIL) select
muxes
(U65,
state of BANKAAVAIL
the Pod processor or the ROM Module
used
the emulation
by
Two of the bank available muxes ICs
mux
opposed to two-to-one
(as
12 and
emulation RAM address
some ROMs, such
The positions of RAM address
and A12.
the placement of
Two other lines, called AI2ENABLE- and A11ENABLE-, are also sent to
U65 and U74.
A12ENABLE- and A11ENABLE- disable address
the RAM Module
is
not driving
Two latches
hold time for address
BCYCLECLK-. The address
latches allow delayed clocking of the address
the Pod
holds
until
next ROM
the
latches are transparent and the addresses pass
latches. Once the BCYCLECLK- goes
last address until the next access.
Board Input/Output Devices
Main
The Main Board input/output device circuitry
Board schematic (Figure
Two data buffers (U102
the output data bus. The buffer outputs drive
latched output ports.
All output ports
received. The clocking signal
of
Each
etc.).
the selected mode (selected
ports are cleared
The ROMIPINXPOL outputs from U85, U54, and pin
polarity of the ROM Module
Control
RAM
5-1).
control of read
switch
the RAM Module(s).
on
write to one bank of emulation RAM while the other
and
the ROM
by
U72, U69, U81, U74, U71, U78,
BANKBAVAIL, either the address lines from
and
RAM.
by the
11
the 2364,
switch pin
as
A12 on the
A11 and
Since some ROM types
hold them
in
and
them.
and U93) delay the ROM address
(U68
traces.
latched
is
the addresses
the outputs
on
Any time the BCYCLECLK- is active
access.
5-1).
U101) pass the data from
and
the output data
on
is an
ports can be written to
the
either
as
a reset or power-up reset
on
address
1
shown
is
write to either bank of
and
normal mode, the Pod
In
The bank available lines
Modules.
mode of the different
the
and U80).
address bus (ROMADDR) are
1
U74) perform a four-to-one
(U65 and
Emulation RAM address
others).
four-to-one mux because
require
the
numbers of address lines
allow software control
12 and
11
ROM.
10
only
use
All
lines
condition while ROM Module
a
stable
lines,
The lines are latched
end of the cycle and held. The
at the
with no penalty since
RAM
DELAY ROMADDR)
(i.e,
straight through the
U68 and U93 latch and hold the
high,
is shown on
page
the
inputs to
the
latched when the proper clock
bus are
output port select (i.e., OUT2-, OUT4-,
a pair or singly, depending on
as
word or byte write). Most of the
a
and all the
outputs
of U86 control the
12
signals that are allowed to pass
bus
9132A Service
2-6.
of
4
the
on
page
the
Depending
on
All
of
address
lines,
and A12 from
1
allowing more
an active
by
the
low,
2-7.
of the
5
Main
Pod data
to
bus
of the Pod's
all
is
go low.
27
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