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The heart of
RESET-
reset
by the
line from
the
BR-, and
BG-
(IPLx) are all tied high through 4.7K-ohm resistors.
the
clocks
(U91)
address decoding
The main
the address space into
the segments begins with a specific letter that identifies its destination.
the line begins with "K",
kernel ROM select or kernel RAM
PMROMSEL- or Personality Module ROM
as
dress, such
as
tion,
such as
output port select (QUTPORTSEL-) and input port select INPORTSEL-).
The port selects from U40
output port decoders,
input port
selects.
bytes,
and can be
selected
can be
The outputs from
from
U73
correspond
provided from the UDS-
is
to write lower
are gated
active during a write cycle if LDS-
forces both data strobes active,
the same
time.
ERAMSEL-
on
ERAMBSEL- through
emulation RAM (ERAM).
RAM
selected
is
The kernel ROM consists of two
The kernel RAM consists of two
Self test enable
access that
is
counted
as a
(ST-LE), the output of U16 pin
enable (ST-OE-) occurs.
access only the self test ports when
Board Sync Generation
Main
The Main Board
Main Board schematic (Figure
block diagram
A
address comparator looks
16-bit
various signals coming onto the main Pod board are, for example,
(The
labeled
ROM1IPIN28
boot ROM coming from the ROM
Pod
68000 microprocessor
the
is a
This line
line.
Mainframe or
the power-up reset RC network. The BERR-,
by
not used during operation.
signals
are
processor.
achieved
is
64K segments. Each of
several
KROMSEL-, the
such as
ARAM-SEL or address RAM
ERAMSEL- or emulation RAM
divided
are
U3
and
is an
input port decoder) into the output port or
Each output port select
written
either
to
the same time or either one can be selected individually).
at
correspond to the high data lines, and the outputs
U83
low data lines. Extra decoding for U83
to the
LDS- lines from
and
(WL-) and
which in
further broken down into ERAMASEL- and
of U40
pin
is
11
These signals
U28.
The state of
low
bank
A, A15 high = bank B).
=
(A15
32K x 8
32K x 8 static
determined
by A23 and
is
interrupt acknowledge occurs while A23
not
an
These accesses pulse self test latch enable
self test access.
13.
These
signals
A23
Timing
generation timing circuitry
sync
5-1).
shown
2-2.
is
in
Figure
or ROMIPIN3.)
(U92).
produced either
is
by
The interrupt
An 8-MHz oscillator
HCT138 (U40). U40 divides
by an
the
refers to kernel,
K
"P" refers to personality,
select.
"A" refers
select.
"E" refers to emula-
select.
U40 also has lines
select.
three ACT138s (U83
by
divided into high
is
byte or a word
as a
(i.e.,
microprocessor, which
the
write upper
WL-
(WU-).
UDS- are active.
and
tum activates WL-
the bank selects for the
are
determines which bank of
AlS5
CMOS ROMs (U90
RAMs
and U88).
(U95
interrupt acknowledge.
If the access
a read, a self test output
is
internal accesses and
disable
all
is
high.
shown
is
Main Board
A
sync
the address lines of ROM Module
at
These
the address lines of the
are
Other types of inputs entering
Module.
9132A Service
The processor is
the PODRESET-
lines
lines that select
If
in
as
such
to ad-
for
and U73
are
low
and
U83 and U73
U73
and
WU-
and
are
word write
A
WU-
and
at
and
U89).
If
any
it
is high,
is
2-4.
2
on
of the
page
generation timing
1.
2-3
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