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9132A Service
from the Personality Module
reaches its maximum value,
SYNCCLK- after
true.
goes
inactive.
the second method,
In
the PAL.
arms
PAL
is
armed,
The
ARM-
of U26A
(DATASYNC). If data
ARM- is issued immediately.
until data
the ROM1
signals are present before
When ARMSEL
ARAM-CLK and ARAM-CLK-
CLK and ARAM-CLK- toggle back to their original values.
and
SSO
of
type
sync state,
signal
state.
The FRC-SYNC line on the
Table 2-1.
SYNC STATE
OFF
IDL
WAIT
DONE
Board
Main
ROM Module
The Main Board ROM Module connections
Board schematic (Figure
J1
connects
connect
in
accesses
the same
card).
Sync Module
The
Sync
The
Sync
UUT microprocessor (eight data
and to drive the cable.
through a protection hybrid (Al),
2-12
used
is
SC11
SC11 is set, the
second rising edge of SYNCCLK-, the SYNC signal goes
On the
RESET-LAT signal from
the
For
method
this
the
same events occur
signal
to the generic PAL
Clock latch (CLKLATCH)
and U9D.
is already valid
sync
goes true. This method eliminates race conditions between
sync
chip select
the data
and
the sync
the PAL
is
on
PAL
SS1 on the
are the sync state signals.
the condition of
is
PAL
State
the Sync State
Definitions for
$51
SS0
DEFINITION
0
0
Disabled,
0
Enabled, waiting
1
condition.
Enabled and armed, waiting for SC11.
1
1
Finished, SC11
0
1
Connections
5-1).
the Pod cable from the 9100
to
ROM Modules
pairs
to
raw Pod processor address
the
found
the Mainframe
as
on
Module schematic diagram
Module
basically a buffer
is
The inputs from the UUT come through J2, pass
the counter clock. When
as
On the first rising edge of
is set.
SYNC signal
the PAL (U32
on
the
work, ARMSEL must
to
occurred
the ARM
as
using
is
created
(U32)
ANDed with data sync
is
clock latch goes
when
If data
not valid, ARM-
sync is
clock,
and
sync
counter clock begins counting.
selected and BCCLK-
When
AC-11
toggle.
SSO and
SS1,
and a
for self
used
test.
Machine
FALSE.
ARMEN IS
first
clocked armed
for
seen
while armed.
are shown on
Mainframe. J4 through
Series
The test connector
through
4.
1
data
and
bus.
board
main
(i.e.,
found
is
in
Figure
5-3.
monitor several of
to
and eight status
lines,
buffer
U3), a resistor pack (Z1, 72)
a
(U2,
the
counter
pin 15)
Personality Module
Once
be low.
the
signal.
the circuit made
in
up
high,
is
delayed
guarantees that both
(pin 10)
true,
goes
goes high, ARAM-
Table
shows the
2-1
definition of the
2-9.
of the Main
7
page
J11
(J16)
This connector
is
for the test access
2-10.
lines
the
to the
control lines)
and
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