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is
(OVDRV-RESET)
(RESETPOL) to determine
determine the polarity of
The processor-specific Personality Module plugs into connector
Personality Module contains two devices, a ROM
the Personality Module is connected to address
lines
0
through
7.
PMROMSEL), the data in the ROM is placed
code
is
uploaded
at
executed.
(The code
the ROM Module is only
word wide to use.)
must
be
The other device in
the
This PAL uses the clock
Other lines going to the PAL are reset request (REQRESET), the
control lines (PSYNCCTLx),
PAL decodes these
lines and
(DATASYNC),
sync
UUT. Another signal
either act the same
as
the timing of the address pulses.
reset
is
detected,
and is
PSYNCCTLx control
for
generic PAL in
the
(BCYCLECLK-). This
the ROM Module
set the
same
as
Personality Module).
The last line going to the Personality Module is called personality present
bar (PM-PRESENT-).
Module
installed. PM-PRESENT- is monitored
is
U20 and U30A make
U20
FAIL) signal.
is
time
active clock edge is received from
an
clock edge within five E clocks, U20 generates a clock fail (CLK-
receive
a
FAIL) signal.
U4D monitors overdrive channel
(880). U4D
off overdrive
twrns
generated. This reduces the amount of time channel
is
pulse
since the Personality Module
is
pulse
generated.
The generic PAL (U32) controls
RAM counter timing. There are two methods of arming the
the first method, ARM is used
In
input to the PAL and arm enable (ARMEN)
signal
is
true, the PAL outputs
(ARMSEL)
are
The SCNT-EN- signal enables
These counters were previously
When the SCNT-EN-
processor.
USB and
through
gated
the overdrive is requested
when
the
reset signal.
When the personality ROM
Pod power-on to
the
not executed directly from the ROM Module since
is
wide,
and
byte
Personality Module
seven channel inputs from the
and
overdrive channel
and
outputs four
signals.
timing signal that shows data bus accesses
a
called sync clock (SYNCCLK-), a line that can
is
the data
can be set
or
sync
RESET-LAT latches true when a UUT
cleared by REQRESET
RESET-LAT
lines.
is
The last signal is bus cycle clock
modes.
some
the same
can
be set
signal
select
1
This signal
grounded whenever the Personality
is
a circuit that generates
up
a timer that continuously resets itself to zero each
the
3
(OVDRVCH3)
(OVDRV3) immediately after the SYNC
3
longer needs OVDRV3 once the SYNC
no
all the sync
as the arm for
the sync
of counters
a set
to a specific value by the Pod
set
signal is
USC along with reset polarity
a PAL. The ROM on
and
lines
through
16
1
selected (using
is
the data
All ROM
bus.
on
Pod RAM where it
main
Pod processor instruction data
the Personality Module
is
Sync
3
(OVDRV3).
One signal
called data
is
to another time
clear mode or by
in
used
initialization or arm
as an
data
or it can be
as
sync,
PAL
input to
the
(an
input port U12 pin
at
UUT clock fail (CLK-
the
UUT. If the circuit does not
state machine
and
is overdriven,
3
counter timing and the address
PAL.
the PAL. When the arm
arm select
and
count enable (SCNT-EN-).
U42, and U2).
(U41,
enabled, the SYNCCLK- signal
9132A Service
also
and
The
J2.
and data
is
PAL.
Module.
sync
The
the
at
show
to
the
the
in
6.
zero
2-11
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