Table of Contents
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GENERAL THEORY OF OPERATION
The 9132A (referred to hereafter
Mainframe
to
the Mainframe and processes the commands
UUT. The 9132
UUT's memory and uses the processor on the UUT to execute the Pod's
commands. To do this, the Pod plugs into or attaches to the UUT Boot ROM
sockets, effectively replacing
for controlling the UUT
To take command or control of
code that originally came from UUT boot
the Pod. This code then executes the user's instructions.
The Pod also monitors some microprocessor lines directly.
timing control (either status or control
microprocessor.
Mainframe or user at a required access
for returning data.
signal
is
functionally return data from the UUT's microprocessor to the Pod
of byte writes
operation occurs, the
the microprocessor data bus into a latch, which
THEORY OF OPERATION
A block diagram of each major Pod
major section
designators such
Section
5.
Signal names appear as
Signal names that end
active state
Board Kernel
Main
The Main Board kernel circuitry
schematic (Figure
Theory
as the
a unit under test (UUT). The Pod receives commands from
a memory emulation Pod, that is,
is
memory in them. The other feature required
the
the
ability to drive or overdrive the UUT
is
the
Basically, these lines form a "sync" signal used by the
Eight data lines are also monitored and
address called a "transfer address".
to an
pulse (generated from
sync
described in the following
is
signal names refer to schematic diagrams
"Uxx"
and
as
NOTE
in
in "-" (e.g., BERR-)
at
low voltage.
is
5-1).
of
Operation
Pod) interfaces the 9100-Series
they can
be
so
takes control of the
it
UUT, the Pod resets the UUT and the
is
ROMs
replaced
monitor
the state
lines)
The other
time.
Pod) loads the data at
the
be read
by
can
is presented in Figure
section
paragraphs.
schematic diagrams.
the
indicate an
of the Main Board
shown
on
page
1
9132A Service
Section
2
2-1.
executed on the
line.
reset
the code from
by
Eight lines
for
of
the UUT
of the
use
sync
means
by
When
this
the Pod.
2-2.
Each
2-1.
Component
in
2-3.
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