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9132A Service
The outputs of the
(ROMBANKSEL)
BANKBAVAIL,
is available to the Pod processor, which bank is available to the ROM
Module, and which bank has readable
RUNUUT
These lines control chip enable
boot ROMs located in the ZIF socket of the ROM Modules. U21A
flip-flop.
RUNUUT
pin
(pin 2)
The flip-flop
line goes
processor
read from
allow
a
occur, dynamically switching the ROM Module
one bus cycle. This switching occurs only if
for
(because
sync
goes active,
mode with the ROM-TST-EN bit
the ROM Modules switch the emulation RAMs out and
lets the UUT
Board Emulation
Main
The Main Board Emulation RAM connectors and self test circuitry are
shown on page
J12,
113,
each ROM Module connected
plugged into these sockets. Each RAM Module has two
into these connectors are bank enable, and address and data lines in
out. The emulation RAM Modules are explained further on
The self test board connector is attached
board.
Self
write,
all
When self test latch enable (ST-LE)
allowing
end of self test, the addresses that
change until
The data path from the self test board connector goes to U100 and U103,
which
are
Pod data bus
test
read).
self
One of the pins
power
when
switch power to the appropriate
K3)
Module.
30, and
SLFTST-CNTL-32) choose which
2-6
flip-flops are ANDed for ROM bank select
U27
bank available (BANKAAVAIL, BANKAAVAIL-,
and
BANKBAVAIL-). These
and
and 4 are separate outputs to ROM Modules
2, 3,
1,
This flip-flop
and
sync counter output (SC11) to
the
the
when
is
swapped
some hardware modes,
true.
(In
not be a true timer signal) The AND/OR gates U4C
to
boot ROM plugged into
the
the only time that data is valid). Once the SYNC line
this is
bus cycle is clocked to Pod
one
read
the data that
processor
Connectors and Self Test
RAM
Board schematic (Figure
of the
3
Main
J14, and J15 are
sockets for
the
to
accessed
test is
when A23 is high.
other address lines go
addresses
the
straight to the different self test pins. At the
to go
next self test
the
access.
noninverting data buffers.
self test output enable
when
ROM Module
on the
plugged into the self
The self test control lines (SLFTST-CNTL-28, SLFTST-CNTL-
lines select which bank
five
bits.
and output enable
(CE)
RUNUUTREQ to the data input
is set by
clock input
the
RUNUUT mode
Pod is in
SC11
can
UUT ROM Module to
the
out of RUNUUT mode
in and
sync
if the Pod
sync
When the clocked bus cycle occurs,
set.
the UUT ROM.
located
in
is
5-1).
emulation RAM Modules. For
the
the Pod, a corresponding RAM Module
a ribbon cable to the self test
by
During self test read or
the address latches U104, U23, and U76.
to
these latches are transparent,
is true,
latched remain stable and do not
are
is
the pins
Whatever
on
is true
(ST-OE)
or 32) must have +5V
(pin 24, 28,
socket.
Three relays
test
depending on the
pin,
is
the
relays
of
and
2,
4.
3,
1,
for the UUT
(OE)
the
is
(pin
3).
pin
the
SC11
and
the
forced
be
by
U37D
and
data
mode is set
to
data sync
is in
ROM in, which
the
2-5.
is
The lines
banks.
and
this section.
in
gated to the
is
during any
(i.e.,
K2,
and
(K1,
of ROM
type
activated.
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