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All input port signals
U98 and U46 are data buffers between
The inputs from the ROM Modules pass through a non-inverting buffer
(U45).
Module designate the size of the ROM Module
ROM Module
monitored
SENT-
set latch (RESET-LAT)
shows the module has
that detects activity on
is a non-clock output from
poses here).
The DELAY ROMADDR
ROM addresses. These addresses return status during certain accesses.
Fa
Board Address
Main
(IDO
sor data
These ports are enabled during an input port select
lines.
(INPORTSEL-)
a read.
and
PROMTYPEI, 2,
determine the
of ROM Module.
type
ROMA4SEL-,
ROM3SEL-, and ROM2SEL- are
ROMISEL-,
output from ROM Module
only.
an
chip selects
1
U45 to determine if
at
ROMIPRESENT-, ROM2PRESENT-, ROM3PRESENT-, and ROM4PRE-
U12 indicate how many ROM Modules are connected to the
on
PM-PRESENT- indicates whether
(CLK-FAIL) comes from a circuit
MAINSTAT and ABORT on U48
lines from
Mainframe.
the
ROM fuse sense (ROMxFUSESENSE) indicate whether
Sync Module and ROM Modules are
Pod data 0 through
7
on
The ROMxPWRFAIL lines show whether power
ROM Modules.
Self test (SFTST-) indicates that a ROM Module is
plugged into the self test socket.
PRSNT-) line indicates that a
socket.
BANKAAVAIL
ERAM bank
swaps.
and Sync
RAM
The Main Board Address RAM and
shown
page 6 of
the
on
The address RAMs (ARAM),
divided into banks of 2K
latch a stream of addresses from ROM Module
analyzer,"
to
Once the address stream is latched, the Pod processor
bits
16
a
time.
at
can access the results using either byte-wide or word-wide reads.
The delayed address (DELAY ROMADDR)
to the ARAM-DATA bus. When
the output port bit ARAM-EN
through ID15)
can be
the
input ports
and 3
are
signals
Headers contained
output enables are active.
and
error exists.
an
Personality Module is present.
the
output from
is an
UUT microprocessor.
a reset
at the
seen
6
on
page
UUT clock
the
line.
Compare equal (COMPAREQ-)
address comparator
the
Ul3
lines
on
are
active high versions of the handshake
are
fuse
Sync
sense
good.
are
input Pod data from the Mainframe.
U11
The self test
Module is plugged into the self test
Sync
BANKBAVAIL monitor the progress of the
and
Interface
Module
Sync
Main Board schematic (Figure 5-1).
and U62,
U61
The ARAM
x 16.
address RAM
the
U56), both
at
9132A Service
read
the Pod processor.
by
and the
microproces-
from ROM Module
the ROM
on
(ie.,
24-, 28-,
or 32-pin).
for self test modes
used
indicating that all of the
1,
ROMISEL-
Personality Module that
the
Clack fail
of the Main Board schematics
for self test pur-
(used
delayed versions of
the
(SYNCFUSESENSE)
fuses on the
the
the indicated
failed
has
on
present (STSYNC-
sync
Module interface circuitry are
static RAMs
8K
x 8
are
used
a "mini
is
as
and store it
1
pass through
U87
can
armed (by enabling
is
U97 are always turned
U87 and
that
1
is
Pod.
Re-
the
and
2-8.
logic
and U97
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