Fluke 9132A Service Manual page 21

9132A Service
through the
earlier in this section).
controls various types of
UB6
Pod
the
to
Arm select (ARMSEL)
Arm enable (ARMEN) enables
don't care (ROMIDC-) goes to
Main Board schematics to determine if ROMISEL-
REARM
(RUNUUTREQ) requests the Pod
latched.
signal is
the Mainframe
but is not sent
The Pod
counter circuitry.
and SLFTST-CNTL-28)
that supply
K3)
The
ROM1PINXDC-
comparator
comparator
All of the outputs of
Modules. These
active chip enable
the pins.
U43, H1,
and Z1 are
U84 controls PODSTAT-
(PODDATAQUT)
in the Pod cable to
Pod data
Mainframe.
Reset polarity (RESETPOL)
driven
high
overdrive.
Swap select (SWAP-SELECT) chooses the mode to clock the bank
pulse.
swaps (either the next BCYCLECLK-
(FRCBANKA)
PLZACCBNKA/-B
(PWRFAIL/PRSENT) informs
(high). If
considers the Pod not present.
ARAM-SEL-0 and ARAM-SEL-1
banks of address
dynamically
to
channel
3
UUT lines
the address RAM
arms
first line of Exclusive OR gates
abort either from COMPAREQ- or from the Mainframe ABORT.
the mode of arming
selects
the
arms CLKLATCH
enable
Sync
cases where
(in
the Mainframe).
to
control lines (PSYNCCTL1-4) on U57 control the
sync
Self test control (SLFTST-CNTL-32, SLFTST-CNTL-30,
on U57
to
the ROM Modules.
power
lines
U75,
on
of Main Board schematics
2
the
on page
bit
is to be
passed or ignored.
U59 (PIN29EN-, PIN29POL-, etc.) go to the ROM
ROM Module
lines tell the
or output enable (OE),
(CE)
used for debug purposes
PODINT-
and
enable
is an
to the
Mainframe.
the
(PODDATAQ through PODDATA7)
on US5
The reset request (REQRESET) line enables the reset
or low.
Force
(FRCSYNC)
sync
force bank
and
the timed
requests
the
power fail line
the is in an
ROM
RAM.
out of RUNUUT
switch in and
(OVDRVCH3) allows
HOLD
(such as a
line)
allow
to it
in the
Enable abort (EN-ABORT) allows
outputs.
the
entire
the
counter circuitry.
sync
address comparator
the
circuitry.
go into RUNUUT mode when
to
controls
(SYNCEN) the sync
signal must be generated internally
a sync
control the self test relays (K1, K2,
U67
and US7 pin 12
,
pins of the ROM are
which
designate the polarity of
and
and are not
the Mainframe.
to
data buffer that drives
U22 is
on
controls whether the UUT reset line
used internally to force the
is
or SCl1).
(FRCBANKB) force bank
B
bank
swap.
Mainframe whether there
invalid or tri-state level, the Mainframe
U56 select one of the four different
on
enable (ROM-TST-EN) allows the
test
a sync pulse. Overdrive
on
Module
the Sync
to
counter activity. ARAM-EN
during
sync
to capture the address trace.
comparator (explained
sync counter
latch,
ROM
1
of the
2
on page
is to be
ignored.
RUNUUT
request
this
output line
to
sync
and
go to the address
determine if
and
the
normally installed.
Pod data
out
data
the lines
:
data sent
the to the
is
sync
Force bank
A
swaps.
Power
present
is a fail
power
Pod
overdrive one of
the