Input Signal Error Detection/Warning Output Settings (Buffer Memory Address 47: Un\G47); Warning Output Flag (Buffer Memory Address 48 :Un\G48) - Mitsubishi Q64AD-GH User Manual

Melsec-q series, programmable logic controller, channel isolated high resolution analog-digital converter module with signal conditioning function
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3 SPECIFICATIONS
3.4.12 Input signal error detection/warning output settings (buffer memory address 47:
Un\G47)
Example
When channel 1 is enabled for process alarm warning output and channel 3 is enabled for
input signal error detection, 0BFE
(Un\G47).
b15
0

3.4.13 Warning output flag (buffer memory address 48 :Un\G48)

3 - 42
(1) This area is used to set whether the input signal error detection/process alarm/rate
alarm warning will be output or stopped on a channel basis.
(2) To make the input signal error detection/warning output settings valid, the
operating condition setting request (Y9) must be turned ON/OFF. (Refer to
Section 3.3.2.)
(3) By default, all channels are set to disable.
b15 b14 b13 b12 b11
0
0
0
Information of b12
to b15 is fixed at 0.
b14 b13 b12 b11 b10
0
0
0
1
CH4 CH3 CH2 CH1
0
(1) If the digital output value or its varying rate falls outside the setting range set to the
CH
process alarm upper/lower limit value (buffer memory addresses 86 to 117:
Un\G86 to Un\G117) or CH
addresses 122 to 137: Un\G122 to Un\G137), the warning output flag for the
corresponding channel turns to 1.
(2) For both the process alarm and rate alarm, whether the warning is for the upper or
lower limit value can be checked on a channel basis.
(3) When the digital output value or its varying rate returns to within the setting range,
the warning output flag is automatically reset.
(4) If the warning is detected on any one of the channels enabled for A/D conversion
and enabled for process alarm or rate alarm warning output, the Warning output
signal (X8) also turns ON.
(5) When the operating condition setting request (Y9) is turned ON, the warning
output flag is cleared.
b15 b14 b13 b12 b11 b10
CH4 CH4 CH3 CH3
Lower
Upper
Lower
limit
limit
limit
value
value
value
b10
b9
b8
0
CH4 CH3 CH2 CH1
Input signal error detection Rate alarm setting
For Q62AD-DGH, information of b2, b3, b6, b7, b10 and b11 is fixed at 0.
(3070) is stored into the buffer memory address 47
H
b9
b8
b7
b6
0
1
1
1
1
CH4 CH3 CH2 CH1
B
F
rate alarm upper/lower limit value (buffer memory
b9
b8
CH2 CH2 CH1 CH1
Upper
Lower
Upper
Lower
Upper
limit
limit
limit
limit
limit
value
value
value
value
value
Rate alarm
For Q62AD-DGH, information of b4 to b7 and b12 to b15 is fixed at 0.
b7
b6
b5
b4
CH4 CH3 CH2 CH1
CH4 CH3 CH2 CH1
Process alarm setting
0: Enable, 1: Disable
b5
b4
b3
b2
b1
1
1
1
1
1
CH4 CH3 CH2 CH1
E
b7
b6
b5
b4
CH4 CH4 CH3 CH3
CH2 CH2 CH1 CH1
Lower
Upper
Lower
Upper
Lower
limit
limit
limit
limit
limit
value
value
value
value
value
Process alarm
0: Normal, 1: Alarm ON
MELSEC-Q
b3
b2
b1
b0
b0
0
0BFE
(3070)
H
b3
b2
b1
b0
Upper
Lower
Upper
limit
limit
limit
value
value
value
3 - 42

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