3 SPECIFICATIONS
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Table 3.7 Buffer memory assignment of Q62AD-DGH (2/3)
Address
Hexadecimal Decimal
38
56
CH2 Digital output value(32Bit) (L)
H
39
57
H
3A
58
H
to
to
System area
3D
61
H
3E
62
CH1 Maximum value(32Bit) (L)
H
3F
63
H
40
64
CH1 Minimum value(32Bit) (L)
H
41
65
H
42
66
CH2 Maximum value(32Bit) (L)
H
43
67
H
44
68
CH2 Minimum value(32Bit) (L)
H
45
69
H
46
70
H
to
to
System area
55
85
H
56
86
CH1 Process alarm lower lower limit value (L)
H
57
87
H
58
88
CH1 Process alarm lower upper limit value (L)
H
59
89
H
5A
90
CH1 Process alarm upper lower limit value (L)
H
5B
91
H
5C
92
CH1 Process alarm upper upper limit value (L)
H
5D
93
H
5E
94
CH2 Process alarm lower lower limit value (L)
H
5F
95
H
60
96
CH2 Process alarm lower upper limit value (L)
H
61
97
H
62
98
CH2 Process alarm upper lower limit value (L)
H
63
99
H
64
100
CH2 Process alarm upper upper limit value (L)
H
65
101
H
66
102
H
to
to
System area
75
117
H
76
118
CH1 Rate alarm warning detection period
H
77
119
CH2 Rate alarm warning detection period
H
78
120
H
System area
79
121
H
7A
122
CH1 Rate alarm upper limit value (L)
H
7B
123
H
1 Indicates whether reading and writing to/from a sequence program are enabled.
R : Read enabled
W : Write enabled
2 When writing data to the buffer memory, always perform write under the interlock conditions (buffer
memory write conditions) of the following I/O signals.
Buffer memory writing conditions
Writing
Operating
Operating
request
condition
condition
setting
setting
request
completed
flag
Description
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
MELSEC-Q
1
Default
R/W
0
R
—
—
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
—
—
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
—
—
2
0
R/W
2
0
R/W
—
—
2
0
R/W
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