Mitsubishi Q64AD-GH User Manual page 52

Melsec-q series, programmable logic controller, channel isolated high resolution analog-digital converter module with signal conditioning function
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3 SPECIFICATIONS
3 - 29
Table 3.6 Buffer memory assignment of Q64AD-GH (2/5)
Address
Hexadecimal Decimal
22
34
CH3 Maximum value(16Bit)
H
23
35
CH3 Minimum value(16Bit)
H
24
36
CH4 Maximum value(16Bit)
H
25
37
CH4 Minimum value(16Bit)
H
26
38
H
to
to
System area
2E
46
H
2F
47
Input signal error detection/warning output settings
H
30
48
Warning output flag
H
31
49
Input signal error detection flag
H
32
50
H
to
to
System area
35
53
H
36
54
CH1 Digital output value(32Bit) (L)
H
37
55
H
38
56
CH2 Digital output value(32Bit) (L)
H
39
57
H
3A
58
CH3 Digital output value(32Bit) (L)
H
3B
59
H
3C
60
CH4 Digital output value(32Bit) (L)
H
3D
61
H
3E
62
CH1 Maximum value(32Bit) (L)
H
3F
63
H
40
64
CH1 Minimum value(32Bit) (L)
H
41
65
H
42
66
CH2 Maximum value(32Bit) (L)
H
43
67
H
44
68
CH2 Minimum value(32Bit) (L)
H
45
69
H
46
70
CH3 Maximum value(32Bit) (L)
H
47
71
H
48
72
CH3 Minimum value(32Bit) (L)
H
49
73
H
4A
74
CH4 Maximum value(32Bit) (L)
H
4B
75
H
4C
76
CH4 Minimum value(32Bit) (L)
H
4D
77
H
4E
78
H
to
to
System area
55
85
H
1 Indicates whether reading and writing to/from a sequence program are enabled.
R : Read enabled
W : Write enabled
2 When writing data to the buffer memory, always perform write under the interlock conditions (buffer
memory write conditions) of the following I/O signals.
Buffer memory writing conditions
Writing
Operating
Operating
request
condition
condition
setting
setting
request
completed
flag
Description
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
(H)
MELSEC-Q
1
Default
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0FFF
R/W
H
0
R
0
R
0
R
0
R
0
R
0
R
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
2
0
R/W
3 - 29

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