Interface Timing; Timing Characteristics; Input Timing Diagram; Power On/Off Sequence - Advantech IDK-2108 Series User Manual

8.4" svga ultra high brightness display kit with led backlight
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3.4

Interface Timing

3.4.1

Timing Characteristics

Table 3.2: Timing Characteristics
Signal
Clock Timing
Vsync Timing
Hsync Timing
Note: Frame rate is 60 Hz.
Note: DE mode.
Note: Typical value refer to VESA standard
3.4.2

Input Timing Diagram

3.5

Power ON/OFF Sequence

VDD power and lamp on/off sequence is as follows. Interface signals are also shown
in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
Parameter
Clock frequency
Period
Vertical
Active
Section
Blanking
Period
Horizontal
Active
Section
Blanking
Symbol
Min.
Typ.
1/ T
33.6
39.8
Clock
T
608
628
V
T
600
600
VD
T
8
28
VB
T
920
1056
H
T
800
800
HD
T
120
256
HB
13
Max.
48.3
650
600
50
1024
800
440
IDK-2108 User Manual

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