Interface Timing; Input Signal Timing Specifications - Advantech IDK-1112P-50XGA1 User Manual

2.7

Interface Timing

2.7.1

Input Signal Timing Specifications

The input signal timing specifications are shown as the following table and timing dia-
gram.
Table 2.7: Display Timing Specifications
Signal
DCLK
Vertical Active Dis-
play Term
Horizontal
Active Display
Term
Note (1) Since this assembly is operated in DE only mode, Hsync and Vsync
input signals should be set to low logic level. Otherwise, this assembly
would operate abnormally.
Note (2) Frame rate is 60Hz
Note (3) The Tv(Tvd+Tvb) must be integer, otherwise, this module would operate
abnormally.
Item Symbol Min.
Frequency Fc 57.5
Total Tv 774
Display Tvd -
Blank Tvb 6
Total Th 1240
Display Thd -
Blank Thb 216
INPUT SIGNAL TIMING DIAGRAM
15
Typ. Max. Unit
64.9 74.4 MHz
806 848 Th
768 - Th
38 80 Th
1344 1464 Tc
1024 - Tc
320 440 Tc
IDK-1112P User Manual
Note
Th=Tvd+Tvb
-
-
Th=Thd+Thb
-