Interface Timing; Input Signal Timing Specifications - Advantech IDK-1110P-50XGB1 User Manual

2.7

Interface Timing

2.7.1

Input Signal Timing Specifications

The input signal timing specifications are shown in the following table and timing dia-
gram.
Table 2.7: Display Timing Specifications
Signal Item
Frequency
Period
Input cycle to cycle
jitter
Input Clock to data
skew
LVDS Clock
Spread spectrum
modulation range
Spread spectrum
modulation
frequency
High Time
Low Time
Frame Rate
Vertical
Total
Display
Active Display
Term
Blank
Total
Horizontal
Display Active Display
Term
Blank
Note (1) Because this module is operated by DE only mode, Hsync and Vsync
input signals should be set to low logic level or ground. Otherwise, this
module will operate abnormally.
Note (2) The Tv(Tvd+Tvb) must be integer, otherwise, the module will operate
abnormally.
IDK-1110P-50XGB1 User Manual
Symbol Min. Typ. Max.
Fc 57.7 65
Tc 13.6 15.4 17.3
Trcl --- ---
TLVCCS -0.02*Tc ---
F
0.987*Fc ---
clkin_mod
FSSM --- ---
Tch --- 4/7
Tcl --- 3/7
Fr --- 60
Tv 776 806
Tvd 768 768
Tvb 8 38
Th 1240 1344 1464
Thd 1024 1024 1024
Thb 216 320
16
Unit Note
73.6 MHz -
ns
200 ns (a)
0.02*Tc ps (b)
1.013*F
MHz (c)
c
200 KHz
--- Tch
--- Tch
--- Hz Tv=Tvd+Tvb
838 Th -
768 Th -
70 Th -
Tc Th=Thd+Thb
Tc -
440 Tc -