Interface Timing; Timing Characteristics - Advantech IDK-1110WP Series User Manual

Note1! "Low" stands for 0V. "High" stands for 3.3V. "NC" stands for "No Con-
nection".
Note1! Interface optional pin has internal scheme as following diagram, Cus-
tomer should keep the interface voltage level requirement which includ-
ing panel board loading as below.
3.4

Interface Timing

3.4.1

Timing Characteristics

The input signal timing specifications are shown as the following table and timing dia-
gram.
Table 3.2: Timing Characteristics
Signal Item
DCLK Pixel Clock
DE Vertical Total Time
Vertical Address Time
Horizontal Total Time
Horizontal Address Time
Note1! Because this module is operated by DE only mode, Hsync and Vsync
input signals should be set to low logic level or ground. Otherwise, this
module will operate abnormally.
IDK-1110WP User Manual
Symbol Min. Typ.
1/T 60.40 71.1
C
T 810 823
V
T 800 800
VD
T 1362 1440
H
T 1280 1280
HD
16
Max. Unit
74.7 MHz
829 T
H
800 T
H
1480 T
C
1280 T
C