Interface Timing; Timing Characteristics - Advantech IDK-2112 Series User Manual

+BLUE5(B5)
+BLUE4(B4)
+BLUE3(B3)
+BLUE2(B2)
+BLUE1(B1)
+BLUE0(B0)
CLK
DE
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
3.4

Interface Timing

3.4.1

Timing Characteristics

Table 3.2: Timing Characteristics
Signal
Clock frequency
Vertical
Section
Horizontal
Section
Note1 Frame rate is 60 Hz.
Note2 DE mode.
IDK-2112 User Manual
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Data Clock
Display Timing
Symbol
1/ T
Clock
Period T
V
Active T
VD
Blanking T
VB
Period T
H
Active T
HD
Blanking T
HB
Blue-pixel Data
Each blue pixel's brightness data consists of
these 6 bits pixel data.
The typical frequency is 40MHz. The signal is
used to strobe the pixel data and DE signals.
All pixel data shall be valid at the falling edge
when the DE signal is high.
This signal is strobed at the falling edge of CLK.
When the signal is high, the pixel data shall be
valid to be displayed.
Min. Typ.
34 40
608 628
- 600
8 28
960 1056
- 800
220 256
14
Max. Unit
48.3 MHz
1024
- T
Line
423
1060
- T
Clock
440