Teac MT-20D-IO Maintenance Manual page 55

CD
The data is written from RAM into the internal register of 2557 by
the
MR(L)
and
roWeL)
outputted from DMAC, and its contents are
outputted over the interface bus (HBO to HB7).
CD
The HOST fetches the data on the interface bus, and outputs ACK.
The handshake timing of REQ and ACK is the same as in Fig. 323.
(]0
DMAC transfers the end byte of one block.
o
When the ACK response is very fast, REQ is set to FALSE, and
interrupt request HINT to CPU is outputted 0.5 clock after (indi-
cated in break line in the figure).
(5) Other transfers
EAch transfer of sense data, status and message is the same as in the
read data transfer. except for the number of transfer bytes.
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