Fig. 320 Vfo Circuit Block Diagram; Fig. 321 Vfo Circuit Timing - Teac MT-20D-IO Maintenance Manual

(3) VFO circuit
In order to sample properly the serial read data. whose period
changes dynamically with fluctuation in the tape speed. the VFO
circuit controls the read clock to keep always the synchronization
with the serial read data.
TP5 TP9
I I
RD
UP(H)
PHASE
LOW PASS
Vc
COMPARA-
FILTER
VCO OUT
TOR
DWN(L)
-
T~2
()
TP4
READ CLOCK
Fig. 320 VFO circuit block diagram
Reference timing (TP5 and TP9) is generated from the serial read data (RD).
Data sample timing (TP2) is also generated by dividing the frequency of the
read clock. The phase difference between these two timings is detected by
the phase comparator. When the data sample timing lags behind the reference
timing. UP(H) pulse is outputted to the following stage; when the former
leads the latter. DWN(L) pulses is outputted to it.
RD
REFERENCE TIMING
DATA SAMPLE TIMING
I I
I
I
UP(H)
____________________
~ ~
____
~nL_
__________
~~----
I
________________________________________
~I
I
U
DWNILl
Fig. 321 VFO circuit timing
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