Host Interface Control; Fig. 322 Selection Operation Timing - Teac MT-20D-IO Maintenance Manual

3-5-4 Host interface control
The hardware of the host interface control consists of a gate array logic IC
(U12/2557 IC, SCSI control) and TTL logic IC (U21, U22) and driver/receiver.
For the details of the interface signal timing. refer to the "MT-2ST/20S
Specifications".
(1) selection operation
TCLK
SEL
BSY
c/o
REO
After setting DMAC for command transfer, the CPU sets the READY F/F
within the 2557 SCSI control (hereinafter, referred to as 2557), and
waits for selection from the HOST.
When such status that SEL is outputted from the HOST together with
the correct ID code and correct parity bit, and none of I/O and BSY
are outputted is maintained during 2.5 to 3.5 clocks BSY is
outputted. Then, after SEL is set to FALSE by the HOST. C/D is
outputted in synchronization with the following clock, and command
phase is generated.
I
I
\\\\\\cb
I
I
I
I
o
I
o
111111
Fig. 322 Selection operation timing
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