Status Model - Stanford Research Systems SIM918 Operating And Service Manual

3 – 24

3.5 Status Model

status registers
Communication Error Status
OVR: Input Buffer Overrun
HWOVRN: Hardware Input Overrun
Event Registers : These read-only registers record the occurrence of defined
Enable Registers : These read write registers define a bitwise mask for their cor-
The SIM918 status registers follow the hierarchical IEEE–488.2 for-
mat. A block diagram of the status register array is given in Figure 3.1.
7 7
DCAS: Device Clear
6 6
CTSH: CTS Halted
5 5
RTSH: RTS Halted
4 4
3 3
2 2
NOISE: Noise Error
1 1
FRAME: Framing Error
0 0
PARITY: Parity Error
CESR CESE
Reference Clock Status
X X
undef
undef X X
X X
undef
X X
undef
3 3
Lock
2 2
Unlock
Arrive 1 1
0 0
Leave
RCSR RCSE
Figure 3.1: Status register model for the SIM918 Precision Cur-
rent Preamplifier.
There are two categories of registers in the SIM918 status model:
events. If the event occurs, the corresponding bit is set to 1.
Upon querying an event register, all set bits within it are
cleared. These are sometimes known as "sticky bits," since
once set, a bit can only be cleared by reading its value. Event
register names end with SR.
responding event register. If a bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set.
Enable register names end with SE.
Standard Event Status
7 7
PON: Power On
URQ: User Request 6 6
5 5
CME: Command Error
4 4
EXE: Execution Error
3 3
DDE: Device Error
2 2
QYE: Query Error
INP: Input Buffer Error 1 1
OPC: Operation Complete 0 0
ESR ESE
Overload Status
X X
undef
X X
undef
X X
undef
X X
undef
undef X X
2 2
Bias + Output
1 1
Output
0 0
Bias
OLSR OLSE
SIM918 Precision Current Preamplifier
Remote Operation
Status Byte
7 7 CESB
-STATUS
6 X MSS
5 5 ESB
4 4 IDLE
3 3 undef
2 2 undef
1 1 RCSB
0 0 OLSB
SB SRE