Status Model; Status Byte (Sb) - Stanford Research Systems SIM984 Operation And Service Manual

2.5 Status Model

2.5 Status Model

Event Registers : These read-only registers record the occurrence of defined
Enable Registers : These read/write registers define a bitwise mask for their cor-

2.5.1 Status Byte (SB)

SIM984 Isolation Amplifier
The SIM984 status registers follow the hierarchical IEEE–488.2 for-
mat. A block diagram of the status register array is given in Figure 2.1.
There are two categories of registers in the SIM984 status model:
events. When the event occurs, the corresponding bit is set
to 1. Upon querying an event register, any set bits within it
are cleared. These are sometimes known as "sticky bits," since
once set, a bit can only be cleared by reading its value. Event
register names end with SR.
responding event register. If any bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set.
Enable register names end with SE.
The Status Byte is the top-level summary of the SIM984 status model.
When masked by the Service Request Enable register, a bit set in the
Status Byte causes the −STATUS signal to be asserted on the rear-
panel SIM interface connector.
Typically, −STATUS remains asserted (low) until a *STB? query is
received, at which time −STATUS is deasserted (raised)
ing the −STATUS signal, it will only be re-asserted in response to a
but see the PSTA command
1
Standard Event Status
PON: Power On 7 7
6 6
URQ: User Request
5 5
CME: Command Error
4 4
EXE: Execution Error
3 3
DDE: Device Error
QYE: Query Error 2 2
1 1
INP: Input Buffer Error
0 0
OPC: Operation Complete
ESR ESE
Figure 2.1: Status Register Model for the SIM984.
Communication Error Status
7 7
DCAS: Device Clear
6 6
CTSH: CTS Halted
5 5
RTSH: RTS Halted
OVR: Input Buffer Overrun 4 4
3 3
HWOVRN: Hardware Overrun
NOISE: Noise Error 2 2
1 1
FRAME: Framing Error
0 0
PARITY: Parity Error
CESR CESE
2 – 13
1
. After clear-
Status Byte
7 7 CESB
-STATUS
6 X MSS
5 5 ESB
4 4 IDLE
3 3 undef
2 2 undef
1 1 undef
0 0 OVLD
SB SRE