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4.5 Status model
4.5 Status model
status registers
Standard Event Status
undef
undef
CME: Command error
EXE: Execution error
DDE: Device error
QYE: Query error
undef
OPC: Operation c omplete
Event Registers : These read-only registers record the occurrence of defined
Enable Registers : These read write registers define a bitwise mask for their cor-
Status Byte : This read-only register represents the top of the status model,
4.5.1 Status byte (SB)
SR124 Analog Lock-In Amplifier
The SR124 status registers follow the hierarchical IEEE–488.2 format.
A block diagram of the status register array is given in Figure 4.1.
5
5
4
4
3
3
2
2
0
0
ESR
ESE
Figure 4.1: Status Model for the SR124 Analog Lock-In Amplifier
There are three categories of registers in the status model of the lock-
in:
events within the lock-in. If the event occurs, the correspond-
ing bit is set to 1. Upon querying an event register, any set bits
within it are cleared. These are sometimes known as "sticky
bits," since once set, a bit can only be cleared by reading its
value. Event register names end with SR or EV.
responding event register. If any bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set in
the Status Byte. Enable register names end with SE or EN.
and is populated with summary bit messages and interface
condition bits. Enabled bits within the Status Byte generate the
remote Request Service event.
At power-on, all status registers are cleared.
The Status Byte is the top-level summary of the SR124 status model.
When enabled by the Service Request Enable register, a bit set in the
Status Byte causes the MSS (Master Summary Status) bit to be set.
Status Byte
7
7
undefined
6
X
MSS: Master Summary Status
5
5
ESB: Event Status Bit
4
4
undefined
3
3
undefined
2
2
undefined
1
1
undefined
0
0
undefined
SB
SRE
4 – 23
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