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3 – 28
Bias
3.5.8 Overload Status Enable (OLSE)
3.5.9 Reference Clock Status (RCSR)
Weight
Bit
Flag
1
0
Bias
2
1
Output
4
2
Bias
8
3
undef (0)
16
4
undef (0)
32
5
undef (0)
64
6
undef (0)
128
7
undef (0)
Bias : Bias overload.
tion 1.2.4.1).
Output : Output overload. Indicates that V
tion 1.2.5).
Output : Transimpedance
V
i
bias
in
Reading this register (with the OLSR? query) clears all overload bits
that are set. If the overload condition persists, the bits will remain
cleared until the overload condition ceases and reoccurs. Use OVLD?
to query the current state of the overload.
The OLSE acts as a bitwise AND with the OLSR register to produce
the single-bit OLSB message in the Status Byte Register (SB). The
register can be set and queried with the OLSE(?) command.
At power-on, this register is cleared.
The Reference Clock Status Register consists of 4 event flags; each of
the flags is set by the corresponding clock event, and cleared only by
reading the register or with the *CLS command. Reading a single bit
(with the RCSR? i query) clears only Bit i.
Weight
Bit
Flag
1
0
Leave
2
1
Arrive
4
2
Unlock
8
3
Lock
16
4
undef (0)
32
5
undef (0)
64
6
undef (0)
128
7
undef (0)
Leave : Reference clock stop detect. Indicates that the external refer-
ence clock signal has ceased.
Output
Indicates that V
bias
stage
overload.
R
10 0 V
F
SIM918 Precision Current Preamplifier
Remote Operation
5 0 V (see also Sec-
10 0 V (see also Sec-
out
Indicates
that
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