Register Model; Status Byte (Sb) - Stanford Research Systems SIM910 Operating Manual

2.5 Register Model

2.5 Register Model

2.5.1 Status Byte (SB)

SIM910 JFET Preamp
The SIM910 monitors and reports errors and other conditions using
a single 8-bit register, the Status Byte register. Each bit in the register
is mapped to a particular event category, and if that event occurs the
corresponding bit is set to 1. Bits in the Status Byte are "sticky," in
the sense that once set to 1, the bit will not revert to the 0 (zero) value
even after the condition that caused the event has completed. Bits
are only cleared by querying the register.
A companion register, the Service Request Enable, acts as a bitwise
mask to the Status Byte for generating the STATUS signal.
This is an 8-bit wide register. It can be read through the *STB?
command which also causes it to be cleared.
Weight Bit Flag
1 0 EXE
2 1 CMD
4 2 QRE
8 3 OVR
16 4 SERR
32 5 URQ
64 6 DCAS
128 7 OVLD
EXE : Execution Error. Indicates an error in a command that was
successfully parsed. Out-of-range parameters are an example.
CMD : Command Error. Indicates a parser-detected error.
QRE : Query Error. Indicates data in the Output Queue has been lost.
OVR : Input Bu er Overrun Error. Indicates data to the Input Bu er
has been lost.
SERR : Serial Communications Error. This can be either (1) an Overrun
Error (indicating received data has been lost), (2) a Noise Error
(indicating noise is present on the receive bits), or (3) a Framing
Error (indicating the stop bit is not detected). Note: A break
signal will not set the SERR bit.
URQ : User Request. Indicates that a button has been pushed.
DCAS : Device Clear. Indicates that a break signal has been received
on the serial interface.
OVLD : Overload. Indicates an overload condition has occurred.
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