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3.5 Status Model
3.5 Status Model
status registers
Event Registers : These read-only registers record the occurrence of defined
Enable Registers : These read write registers define a bitwise mask for their cor-
SIM983 Scaling Amplifier
The SIM983 status registers follow the hierarchical IEEE–488.2 for-
mat. A block diagram of the status register array is given in Figure 3.1.
Communication Error Status
DCAS: Device Clear
CTSH: CTS Halted
RTSH: RTS Halted
OVR: Input Buffer Overrun
HWOVRN: Hardware Input Overrun
NOISE: Noise Error
FRAME: Framing Error
PARITY: Parity Error
Standard Event Status
PON: Power On
URQ: User Request
CME: Command Error
EXE: Execution Error
DDE: Device Error
QYE: Query Error
INP: Input Buffer Error
OPC: Operation Complete
Overload Status
undef
undef
undef
undef
undef
Output
Input + Offset
Input
Figure 3.1: Status register model for the SIM983 Scaling Amplifier.
There are two categories of registers in the SIM983 status model:
events. If the event occurs, the corresponding bit is set to 1.
Upon querying an event register, all set bits within it are
cleared. These are sometimes known as "sticky bits," since
once set, a bit can only be cleared by reading its value. Event
register names end with SR.
responding event register. If a bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set.
Enable register names end with SE.
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
CESR
CESE
Status Byte
7
7
6
6
7
7
CESB
5
5
6
X
MSS
4
4
5
5
ESB
3
3
4
4
IDLE
2
2
3
3
undef
1
1
2
2
undef
0
0
1
1
undef
ESR
ESE
0
0
OLSB
SB
SRE
X
X
X
X
X
X
X
X
X
X
2
2
1
1
0
0
OLSR
OLSE
3 – 19
-STATUS
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