Programmable Timers; Interval Timers - Motorola MVME2603-1121A Installation And Use Manual

Block Diagram
3

Programmable Timers

Interval Timers

3-14
A 28-pin 330mil SO device containing the real-time clock, the
oscillator, power failure detection circuitry, timer logic, 8KB
of static RAM, and gold-plated sockets for a battery
A SNAPHAT battery housing a crystal along with the battery
The SNAPHAT battery package is mounted on top of the
M48T59/T559 device. The battery housing is keyed to prevent
reverse insertion.
The clock furnishes seconds, minutes, hours, day, date, month, and
year in BCD 24-hour format. Corrections for 28-, 29- (leap year),
and 30-day months are made automatically. The clock generates no
interrupts. Although the M48T59/T559 is an 8-bit device, 8-, 16-,
and 32-bit accesses from the ISA bus to the M48T59/T559 are
supported. Refer to the MVME2603/2604 Programmer's Reference
Guide and to the M48T59/T559 data sheet for detailed
programming and battery life information.
Among the resources available to the local processor are a number
of programmable timers. Timers are incorporated into the PIB
controller and the Z8536 CIO device (diagrammed in
Figure 3-1). They can be programmed to generate periodic
interrupts to the processor.
The PCI-ISA Bridge controller has three built-in counters that are
equivalent to those found in an 82C54 programmable interval
timer. The counters are grouped into one timer unit, Timer 1, in the
PIB controller. Each counter output has a specific function:
Counter 0 is associated with interrupt request line IRQ0. It
can be used for system timing functions, such as a timer
interrupt for a time-of-day function.
Counter 1 generates a refresh request signal for ISA memory.
This timer is not used in the MVME2603/2604.
Figure 1-1 and