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IDStructlon
Set
8-Bit
Load
Group
The 280 microprocessor has one of the most
powerful and versatile instruction sets
available in any B-bit microprocessor. It
includes such unique operations as a block
move for fast, effiCient data transfers within
memory or between memory and
va.
It also
allows operations on any bit in any location in
memory.
The following is a summary of the
Z80
instruction set and shows the assembly
language mnemonic, the operation, the flag
status, and gives comments on each instruc-
tion. The ZaD CPU Technical Manual
(03-0029-01)
and Assembly Language
Programming Manual
(03-0002-01)
contain
Significantly more details for programming
use.
The instructions are divided into the
follOWing categories:
DB-bit loads
o
I6-bit loads
o
Exchanges, block transfers, and searches
DB-bit arithmetic and logic operations
o
General-purpose arithmetic and CPU
control.
Symbolic
F1agn
-
0p0rat10il
B
Z
H
PlY
n
C
LOr. r'
r - r'
X
0
X
0
LOr. n
X
X
0
lO" (HL)
, - (HL)
y.
0
X
·
0
LD., (lX+d)
, - (!X+d)
X
X
lO '. (lY +d)
, - (IY+d)
X
lO(HL).•
(HL) - .
X
0
lO(lX+d), •
(lX+d) - r
X
lO (lY +dl, •
(lY+d) - .
0
0
X
0
X
·
lO (HL), n
(HL) - n
0
0
X
0
X
0
lO (lX+d), n
(lX+d) - n
0
0
X
0
X
0
lO (lY +d). n
(lY+d) - n
0
·
X
0
X
·
lOA, (Be)
A - (Bel
· ·
X
·
X
·
LDA, (DE)
A - (DE)
· ·
X
·
X
·
LOA.
(nn)
A -
(no)
X
·
X
·
LDlBe), A
(BCI - A
· ·
X
0
X
0
LD(DEI, A
(DE) - A
X
·
X
0
LDlnnl. A
(nn) -A
·
·
X
·
X
·
LDA.I
A -I
X
0
X IFF 0
.
LDA. R
A-R
,
X
0
X IFF 0
0
lOl. A
1- A
X
0
X
LDR; A
R-A
0
·
X
0
X
NOTES: r.
f '
meAn. any oilhe' rttqi.ters A. B. C. O. E. H. L.
IFF ItMt conlenl o! the- anterrupt /finable Ihp·llop, (IFF)
II
copHtd Into 1M-
P.-V Uag.
For lin ellpl4MlLon f')f
llaQ
nolallon and Iymbols
IOf
mnemonic t.!lble•.
Me!
Symbolic Notallon
~hon
folloWlf.Q
IdblM.
o
i6-blt arithmetic operations
o
Rotates and shifts
o
Bil
set, reset, and test operations
o
Jumps
o
Calls, returns, and restartS
o
Input and output operations
A
variety of addressing modes are
implemented to permit efficient and fast data
transfer between various registers, memory
locations, and input/output devices. These
addressing modes include:
o
Immediate
o
Immediate extended
o
Modified page zero
o
Relative
o
Extended
o
Indexed
0
Register
o
Register indirect
o
Implied
o
Bit
Opcode
110.01 110.0111 110.01 T
,. sa
liD II.. 8ytoo
Cycloo s_
e - -..
01
,
"
~
00
,
110
- n -
001
C
01
,
110
7
010
D
11 011 101
DD
19
011
E
01
,
101
100
H
- d -
101
L
11 III 101
FD
19
III
A
01
,
110
- d -
Ol 110
,
7
11 011 101
DD
19
01 110
,
- d -
11 III 101
FD
19
01 110
,
- d -
00 110 110
36
10
- n -
Il 011 101
DD
19
00 110 110
36
- d -
- n -
Il III 101
FD
19
00 110 110
36
- d -
- n -
00 001 010 01.
I
7
00 011 010
11.
I
7
00 ill 010 31.
3.
13"
":"" n'-
- n -
00 000 010
02
2
7
00 010 010
12
2
7
00 110010
:J2
4
13
- n -
- n -
Il 101 101
ED
01 010 III
57
11 101 101
ED
01 Oil III
5F
11 101.101
ED
01 000 III
47
11 101 101
ED
01 001 III
4F
2OO1.()()1
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