Table of Contents
Advertisement
latched mto the appropriate regIster with the
rising edge of clock cycle TWA. No edditional
wait st"tes "re allowed.
Timing
Read Cycl/t Timing. Figure 9 shows re"d
:::ycle timing. This cycle re"ds the contents of a
down-counter without disturbing the count.
During clock cycle T2, the Z-80 CPU initiates "
read cycle by driving the following inputs
Low: RD, IORQ, and CEo A 2-bit binary code
at inputs CSI and CSo selects the channel to
be read. M1 must be High to distinguish this
cycle from an interrupt acknowledge. No addi-
tional wait states are allowed.
IIITaIIAL
T I _
_
- '
S'f"f'TllNIHO
Figure 9. Read eycl.. Timing
Figure 11. nme. Mode Timing
ZC'TO
- '
Figure 12. Counter Mode Timing
Timer Operation. In the timer mode, a
CLK/TRG pulse input starts the ·timer (Figure
11) or; tl-e second succeeding rising edge of
CLK. Tic, trigger pUlse is asynchronous. and it
must ha \'e a minimum width. A minimum lead '
time (210 ns) is required between the active
edge of the CLK/TRG and the next rising edge
of CLK
l.:J
enable the prescaler on the follow-
ing clock edge. If the CLK/TRG edqe occurs
closer than this, the initiation of the timer
function is delayed one clock cycle. This cor-
responds to the startup timing discussed in the
programming section. The timer can also be
started automatically if so programmed by the
channel control word.
CLKIT"'O
BNTI!RHA.L
COll"UR
-----'1
T,
T,
T,
CLK
-
--.,.--------------
II'
,
_J
DATA
----------l
Write Cycle Timing. Figure 1Cl shows write
cycle timing for loading control. time constarlt
or vector words.
The CTC does not have a write signal input,
so it generates one internal:y when the read
(RD) hput is High during Tl. During T
2
IORQ and CE inputs are Low. M1 must be
High to d;stinguish a write cycle from an inter-
"Upt acknowledge.
A
2-bit binary code at
inputs CSI and CSo selects the channel to be
addressed, and the word being written is
p;aced on the Z-80 data bus. The data word is
Ctlo, CS1,
Ci
::=x:
CHANNEL ADDRESS
x==
'ORO
\
r -
AD
\
r -
Figure 10. Write Cycle Timing
---.,..------
..,
I
.'"
--T--------------
iUS
I
_J
Counter Operation. In the counter mode, the
CLK/TRG pulse input decrements the down-
counter. The trigger is asynchronous, but the
count iE synchronized with CLK. For the
decrement to occur on the next rising edge
01
CLK. the trigger edge must precede CLK by "-
minimum lead time as shown in Figure 12. If
the lead time is less than specified, the count
is delayed by one clock cycle. The trigger
pulse must have a minimum width, and the
trigger period must be at least twice the clock
period.
The ZC/TO output occurs immediately after
zero count, and follows the rising CLK edge.
DAT"
X
CSQ, C!S1,
Ci
==.x
CHANNEL
'-~ORESS
c=.=
'ORO
\
r--
2041-0162.0163.0164.0165
Advertisement
Table of Contents
