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~
i:i
Comment.
Dr
De
Os
D4
D3
D2
D,
Do
HEX
WRO selS OMA 10 receive
0
1
1
1
1
0
0
I
1
79
block lenglh, Pori A slarl,
Block Lenglh
Block Lenglh
PoriA
Pori A
B _ A
109 address and lemporarily
Upper
Lower
Upper
Lower
Temporary
Transler, No Search
sets Pori B as source.
Follows
Follows
Address
Address
for
Follows
FOllows
Loading B
Address~
Pori A address (lower)
0
1
0
I
0
0
0
0
50
Port A address (upper)
0
0
0
1
0
0
0
0
10
Block lenglh (lower)
0
0
0
0
0
0
0
0
00
Block lenglh (upper)
0
0
0
1
0
0
0
0
10
WRI defines Port A as
0
0
0
1
0
1
0
0
14
memory
with
lixed
No Timing
Address
Address
Port is
incrementing address.
Follows
Changes
Increments
Memory
WR2 delines Port B as
0
0
1
0
1
0
1
0
28
peripheral wilh lixed
No Timing
Fixed
PorI is
address.
Follows
Address
1/0
WR4 sels
mode
10 Bu rsl,
1
1
0
0
0
1
0
1
C5
sels OMA 10 expecl Pori B
No Inlerrupl
No Upper
Pori BLower
address.
Bursl Mode
Conlrol Byte
Address
Address
Follows
FOllows
Pori B address (lower)
0
0
0
0
0
1
0
1
05
WR5 sels Ready active High.
1
0
0
0
1
0
1
0
8A
NO AulO
No Wail
ROY
Reslarl
Slales
Aclive High
WR6 loads Por' B address
1
1
0
0
1
1
1
1
CF
and resels block counter.
a
WRO
sets
Port A as source.
a
0
0
0
0
0
1
0
1
05
No Address or Block
A _ B
Transfer, No Search
Lenglh Bytes
WR6 loads PorI A address
1
1
0
0
I
1
1
1
CF
and resels block counler.
WRB enables OMA 10 slarl
1
0
0
0
0
1
1
1
87
operation
NOTE: The aclual number of bytes Iranslerred
is
one more Ihan specified by Ihe block length.
'These enlries .re necessary only in lhe case of a lixed destination address.
Figun 9. Sample DIU
Program
naoa
If
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