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Inactive
State Timing
(DMAas CPU
Peripheral)
Active State
Timing
(DMAas Bus
Controller)
In its disabled or inactive state, the DMA is
addressed by the CPU as an I/O peripheral for
write and read (control and status) operations.
Write timing is illustrated in Figure 10.
Reading of the DMA's status byte, byte
counter or port address counters is illustrated
eLK
r
'+--'-
-+-- - - - -
00-07
-4--+--(
Figure 10. CPU-Io-DMA Wrile Cycle
Default Read' and Write Cycles. By default,
and after reset, the DMA's timing of read and
write operations is exactly the same as the 2-80'
CPU's timing of read and write cycles for
memory and I/O peripher'als, with one excep-
tion: during a read cycle, data is latched on
the falling edge of T
3
and held on the data bus
across the boundary between read and write
cycles, through the end of the following write
cycle.
Figure 12 illustrates the timing for memory-
to-I/O port transfers and Figure 13 illustrates
I/O-to-memory transfers. Memory-to-memory
and I/O-to-I/O transfer timings are simply per-
mutations of these diagrams.
The default timing uses three T-cycles for
memory transactions and four T-cycles for I/O
transactions, which include one automatically
in Figure II. These operations require less
than three T-cycles. The CE, IORQ and
RD lines are made active over two rising edges
of CLK, and data appears on the bus approx-
imately one T-cycle after they become active.
eLK
C i ~
_
lORQ
AD
- - -
00-07
Figure II. CPU-Io-DMA Read Cycle
inserted wait cycle between T
2
and T
3 .
If the
CE/WAIT line is programmed to act as a
WAIT line during the DMA's active state, it is
sampled on the falling edge of T
2
for memory
transactions and the falling edge of T
w
for I/O
transactions. If CE/WAIT is Low during this
time another T-cycle is added, during which
the CE/WAIT line will again be sampled. The
duration of transactions can thus be indef-
initely extended.
Variable Cycle and Edge Timing. The Z-80
DMA's default operation-cycle length for the
source (read) port and destination (write) port
can be independently programmed. This
variable-cycle feature allows read or write
cycles consisting of two, three or four T-cycles
(more if Wait cycles are inserted), thereby
increasing or decreasing the speed of all
signals generated by the DMA. In addition,
I
"'--MEMORYREAD~lfOWRITE
_I
T,
I
~
I
h
I
.~
I
~
I
~
~
eLI(
Ao-A'IJ
--I
MREQ
iiC
_nl
fciiii
WR
00-D7
CilwAIT
rL
r - -
rLrL
"'-
~
,-",-
r - -
-
" -
II
II
II
-
1\
I
-
\
I
r
I--
1\
r
-
\
-
---,
MEMORY
-
- - J
DRIVES DATA
DATA
sus
DRI
NI
DMA
-
--
f.f==
---
f---
-- -
-
--
--
--
I
'l
1---
-
.
Figure 12. Memory-la-I/O Tranafer
2032-0134, 0135, 0136
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