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Figure 13. Datsr-ChaID Il1t-upt PrlorIU..
The 2-80 CTC follows the 2-80 system inter-
rupt protocol for nested priority interrupts and
return from interrupt, wherein the interrupt
priority of a peripheral is determined by its
location in a daisy chain. Two lines-IEI and
lEO-in the CTC connect it to the system daisy
chain. The device closest to the
+
5 V supply
has the highest priority (Figure 13). For addi-
tional information on the 2-80 interrupt struc-
ture, refer to the Z-80 CPU Product Specifica-
tion and the Z-80 CPU Technical Manual.
were written to the CTC during the program-
ming process; the next two bits are provided
by the CTC interrupt control logic as a binary
code that identifies the highest priority chan-
nel requesting an interrupt; the low-order bit
is always zero.
Interrupt Acknowledge Timing. Figure 14
shows interrupt acknowledge timing. After an
interrupt request, the 2-80 CPU sends an inter-
rupt acknowledge (Ml and IORO). All chan-
nels are inhibited from changing their inter'
rupt request status when MI is active-about
two clock cycles earlier than IORO. RO is
High to distinguish this cycle from an instruc-
tion fetch.
The CTC interrupt logic determines the
highest priority channel requesting an inter-
rupt. If the CTC interrupt..enable input (lEI)
lS
High, the highest priority interrupting channel
within the CTC places its interrupt vector on
the data bus when IORO goes Low. Two wail
states (TWA) are automatically inserted at this
time to allow the daisy chain to stabilize. Addi-
tional wait states may be added.
Return from Interrupt Timing. At the end of
an interrupt service routine the RET! (Return
From Interrupt) instruction initializes the daisy
chain enable lines for proper control of nested
priority interrupt handling. The CTC decodes
the 2-byte RETI code internally and determines
whether it is intended for a channel being ser-
viced. Figure 15 shows RET! timing.
If several 2-80 peripherals are in the daisy
chain, IEI settles active (High) on the chip
currently being serviced when the opcode
E016 is decoded.
If
the following opcode is
4016, the peripheral being serviced is released
and its IEO becomes active. Additional wait
states are allowed.
LOWRIT PRIORITY
IDIVICR
Within the 2-80 CTC, interrupt priority is
predetermined by channel number: Channel 0
has the highest priority, and Channel 3 the
lowest. If a device or channel is being serviced
with an interrupt routine, it cannot be inter-
rupted by a device or channel with lower
priority until service is complete. Higher
priority devices or channels may interrupt the
servicing of lower priority devices or channels.
A 2-80 CTC channel may be programmed to
request an interrupt every time its down-
counter reaches zero. Note that the CPU must
be programmed for interrupt mode 2. Some
time after the interrupt request, the CPU sends
an interrupt acknowledge. The CTC interrupt
control logic determines the highest priority
channel that is requesting an interrupt. Then,
if the CTC lEI input is High (indicating that it
has priority within the system daisy chain) it
places an 8-bit interrupt vector on the system
data bus. The high-order five bits of this vector
HIOH••T PRIORITY
Davie..
11lI:::::::'/
'1.-
---11
',-_.... 1
T,
,.,-
-
-
- -
- -,,..----------
_ _ _ _ _ _ J
Oo-D,---(
CLK
~:=:=
TWA
TWA
T,
!iii
CLK
DATA
---------_..(~)----
••0
r-
- - -
-....,1
Figure 14. IDterrupt killlo_ledge TlmlDg
Figure 15. Retum From Il1terrupt Tlmll1g
2041·0166.0167.0168
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