ADC SUPER SIX S-100 Technical Manual page 76

Functional
Description
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The Z-80 CTC has four indepe'1dent c::unterl
timer channels. Each channel
;5
individ'lally
programmed with two words: a con~rol word
and a time· constant word. The control wore
selects the operating mode (counter or timer).
enables or disables the channel interrupt, and
selects certain other operating parameters. If
the timing mode is
selec~ed,
tl1e control word
also sets a prescaler, which civides the system
clock by either 16 or 256. The time· constant
word is a value from 1 to 256.
During operation, the .,ndividual counter
channel counts down from the preset time con-
stant value. In counter mode operation the
counter decrements on each of the CLKlTRG
input pulses until zero count is reac:1ed. Each
decrement is synchror:ized by the system
clock. For counts greater than 256, more than
one counter can be cascaded. At zero count,
the down-counter is autoI::la~ally reset with
the time constant value.
The timer mode determines time intervals as
small as 4
p.s
(Z-80A) or 6.4 p.s (Z-80) without
additional logic or software timing loops. Time
intervals are generated by dividing the system
clock with a prescaler that decrements
The CTC has four major elerr.ents, as shown
in iigure 3.
• CPU bus 1/0
• Channel control logic
• Interrupt logic
• ::::ounterltimer circuits
CPU
BUB
I/O. The CPU bus I/O circuit
decodes the address inputs, and interfaces the
CPU data and control sigr:als to the CTC lor
distribution on the internal bus.
a p,eset down-counter.
Thus, the time interval is an integral mUl-
tiple of the clock period, the prescaler value
(16 or 256) and the time constant that is preset
in the down-counter. A timer is triggered auto-
matically when its time constant value is pro-
grammed, or by an external CLKlTRG input.
Three channels have two outputs that occur
at zero count. The first output is a zero-
count/timeout pulse at the ZC/TO output. The
fourth channel (Channel 3) does not have a
ZC/TO output; interrupt request is the only
output available from Channel 3.
The second output is Interrupt Request
(INT). which occurs if the channel has its
interrupt enabled during programming. When
the Z-80 CPU acknowledges Interrupt Request,
the Z-80 CTC places an interrupt vector on the
data bus.
The four channels of the 2-80 CTC are fully
prioritized and fit into four contiguous slots in
a standard Z-80 daisy-chain ;nt~rrl1!"lt ~trll('­
ture. Channel 0 is the highest priority and
Channel 3 the lowest. Interrupts can
be
individually enabled (or disabled) for each of
the four channels.
Internal Control Logic. ":'he CTC internal
control logic controls ove~all chip operating
functions such as the chip enable, reset, anC
read/write logic.
Interrupt Logic. The interrupt control logic
ensures that the CTC inte~rupts interface prop-
erly with the Z-80 CPU ir.terrupt system_ The
logic controls the interrupt priority of the CTC
as a function of the IEI signal. If IEI is High,
the CTC has priority.
DlA.ir.g
;i"~;,-upt
{
DATA
,.-
z.o
C""
CONTROL
iiii
' "
lED
ZCl!O
CU<tT1lG
Figure 3. Funcllc....1 llcel< DlagraJll
2041-0157