ADC SUPER SIX S-100 Technical Manual page 71

Single board computer
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Z-IO
PIO
z..tIOA.
r.o
z.«a
PIOI91
MIJ1
Max
IIlD
Max
Mia
Max
NumbeI' Symbol
Parcmaeter
(-)
(1lIlI1
(1lIlI1
h:llll
(-I
(1lIlI1
1
TcC
Clock Cycle Time
400
[I]
250
[I]
165
[II
2
TwCh
Clock Width (High)
170
2JOO
lOS
2JOO
65
2JOO
3
TwCI
Clock Width
(Low)
170
2JOO
105
2000
65
2000
4
TIC
Clock Fall Time
30
30
20
5-TrC
Clock Rise Time
30
30
20
6
TsCS(Rl)
CE,
alA,
cm
to RD,
IORQ I Setup Time
50
50
50
161
'1
Th
Any Hold Times lor Specified
Setup Time
0
0
0
0
8
TsRI(C)
ID5,
IORQ to Clock
t
Setup
Time
115
115
70
9 - TdRI(DO)--RD, IORQ Ito Data Out Delay
430
380
300
12]-·-
10
TdRI(DOs)
RD, IORQ I to Data Out Float
Delay
160
110
70
Ii
II
TsDI(C)
Data In to Clock t Setup Time
50
50
40
CL
=
50 pF
12
TdIO(DOl)
fORQ I to Data Out Delay
(INTACK Cycle)
340
160
120
[3]
S
13- TsMI(Cr)-- MI I to Clock
t
Setup Time-- 210
90
70
14
TsMl(Cl)
MI-Lto Clock I Setup Time
(MI Cycle)
lJ
0
0
[81
15
TdMI(1EO)
MI I to lEO I Delay
(Int~upt
Immediately Preceding MI
I)
300
190
100
(5,71
16
TsIEI(IO)
IEI to IORQ I Setup Time
(INTACK Cycle)
140
140
100
(7]
17 -
TdIEI(IEO/)- lEI I to lEO I Delay
190
130
120
( 5 ] -
CL
=
50 pF
18
TdIEI(IEOr)
IEI
t
to lEO I Delay (alter ED
Decode)
210
160
160
[5]
19
TcIO(C)
IORQ
t
to Clock I Setup Time
(To Activate READY on Next
Clock Cycle)
220
200
170
20 -
TdC(RDYr)-- Clock I to READY
t
Delay--- 200
190
170
[5]---
CL
=
50 pF
21
TdC(RDYI)
Clock I to READY I Delay
150
140
120
[5]
22
TwSTB
~
Pulse Width
150
150
120
(4]
23
TsSTB(C)
~
t
to Clock I Setup
Time (To Activate READY on
Next Clock Cycle)
220
220
150
[5J
24 -TdIO(PD)-- IORQ
t
to PORT DATA Stable
Delay (Mode 0)
200
180
160
[5]
25
TsPD(STB)
PORT DATA to
~
t
Setup Time (Mode I)
260
230
190
26
TdSTB(PD)
~
I to PORT DATA
Stable (Mode 2)
230
210
180
[5]
27 --TdSTB(PDr)-S'I'iiDBE t to PORT DATA Float
Delay (Mode 2)
200
180
160
CL
=
50 pF
28
TdPD(INT)
PORT DATA Match to INT I
Delay (Mode 3)
540
490
430
29
TdSTB(INT)
~
t
to
nrr
I Delay
490
440
350
!'lOTES:
16) T.cS(RI) mdY be reduced. However, the time oubtrdcted
(II TcC
=
TwCh + TwCl + TrC + TIC.
lrom T.cS(Rl) will be ddded
10
TdRI(OO).
(2] Increase TdRI(DO)
by
10 ns for each 50 pF increase in l04d
(71 2.5 TcC
;>
(N-2)TdIEI(lEOf) + TdMl(lEO) + ToIEI(lO)
up to
200
pF max.
+ TTL Buffer Deldy,
if dny.
13) Incredse TdIO(OOl) by 10 no lor edch 50 pF. increese in
18)
lli
must
be
active for a minimum of two clock. cycles to
loading up
10
200 pF mex.
reset the PIO.
(4) For Mode 2: TwSTB
;>
TsPD(STB).
191 ZSOB PIO numbers dre prelimindry dnd oubject to chdnge.
151 Increase these values by 2 ns for each 10 pF Increase In
loadtng up
10
100 pF me•.

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