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Actl". State
TimlDg'
(DNA as
BWI
Controller)
(Continued)
----""
......
-----'
cur.
......,.
-i"---+--+-+-+--+A--4-+-+--~-
Figure 13. IIO-to-Memory Tranal..
i
I
the trailing edges of the RJRQ,
MRED,
RD and
Wfl:
signals can be independently terminated
one-half cycle early. Figure 14 illustrates this.
In the variable-cycle mode, unlike default
liming,
iC5RQ
comes active
one-~cle
before MREQ, RD and WR. CElWAIT can be
used to extend only the 3 or 4 T-cycle variable
memory cycles and only the 4-cycle variable
I/O cycle. The CElWAIT line is sampled at the
falling edge of T
2
for 3- or 4-cycle memory
cycles, and at the falling edge of T
3
for 4-cycle
I/O cycles,
During transfers, data is latched on the
clock edge causing the rising edge of RD and
held through the end of the write cycle.
BWI
RequHtll. Figure 15 illustrates the bus
request and acceptance timing. The RDY line,
which may be programmed active High or
Low, is sampled on every rising edge of CLK.
If it is found to be active, and if the bus is not
In use by any other device, the following rising
edge of CLK drives BUSREQ low. After receiv-
.!llil
BUSREQ the CPU acknowledges on the
BM input either directly or through a
multiple-DMA daisy chain. When a Low
iii
detected on BAI for two consecutive rising
edges of CLK, the DMA will begin transferring
data on the next rising edge of CLK.
Figure 14. VariableoCyc:1et and Edge TIJD!Dg
2032·0131. 0138. 0139
- -
-
" """"
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