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CPU
Timing
(Continued)
Halt Aclmow1edge Cycle. When the CPU
receives a
HALT
Instruction,
It
execute.
NOP
states until either an
rnT
or
m:;rr
Input
is
received.
When
in the Halt Itate, the
lIMT
output
t.
active and remains
110
until an inter-
rupt II
proceaed
(Figure 11).
M1
_I'
..
..,.
..
C L O C K ~ T '
T,
T,
T,
T,
T,
T,
•
•
iiii:T : : : : :
R _ ~ _ '
_ _
.M.
U-
NOTE: INT w'ill also force a Halt exit.
~See
note, Figure 9.
Figure II. Halt Acknowledge Cycle
Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly
accept it. As long as RESET remains active', the
address and data buses float, and the control
outputs are inactive. Once RESET goes
inactive, two internal T cycles are consumed
before the CPU resumes nor'mal processing
operation.
lffiSlIT
clears the PC register, so the
first opcode fetch
will
be to location
ססoo
(Figure 12).
k - - - M ' - - - - - -
T,
T,
CLOCK
""-A1·=======P---,,(I---~~---+-C====
Do-D7
------------
lin
- ' /
~
:_-----Z..,..ZT'l!r-7V..,..Z"T"7---....,·f'.IJ. . - -------':.
:.:.:.-_-_-_-=
HALT
2005-887.
888
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