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Pin
DetIcrIptlon
(Continued)
MI. Machine Cycle (Input from CPU, active
Low). This signal is used as a sync pulse to
control several internal PIa operations. When
both the Ml and RD signals are active, the
Z·BO CPU is fetching an instruction from
memory. Conversely, when both MI and
IORQ are aelive, the CPU is acknowledging
an interrupt. In addition, Ml has two other
funelions within the
Z·80
PIO: it synchronizes
The following timing diagrams show typical
timing in a Z-BO CPU environment. For more
precise specifications refer to the composite
ac timing diagram.
Writ.
Cyc1••
Figure 12 Illustrates the
timing lor programming the Z·BO PIa
or for writing data to one of Its ports. No
Walt states are allowed for writing to the
PIa other than the automatically Inserted
TWA. The PIa does not receive a speci-
fic write signal;
It
Internally generates
Its own from the lack. of an active
RD signal.
the PIa interrupl129ic; when Ml occurs
without an active RD or IORQ signal, the PIO
is resel.
RD. Read Cycle Status (input from
Z-80
CPU,
active Low). If RD is aelive, or an 1/0 opera-
tion is in progress, RD is used with BfA,
ciD,
CE, and 10RQ to transler data lrom the
Z·80
PIO to the
Z-80
CPU.
T,
T,
T••
T,
T,
CI.J(
Cl6,IIIA
:::x
x==::
CI
\
r-
ilIiR
DATA
X
III
x:=
n·
\
r-
·Wi •
RD.
~
•
Cii5 • iOiiQ
Flgur.12. Wrlw CycI- TImlng
RltGd. Cyd.. Figure 13 Illustrates the timing
T,
T,
T••
T,
T,
for reading the data Input from an external
device to one of the Z·BO PIO
pOrts.
No Walt
eLl(
states are allowed for reading the PIa other
CIIi,lIIi
=x
x=
. than the automatically Inserted TWA.
Output
M~ (M~
0). An output cycle
CI\
r
(Figure 14) Is a!ways started by the execution
of an output Instruction by the CPU. The WRo
\
r
pulse from the CPU latches the data from the
il5H
CPU data
bus~o
the selected port's output
r
register. The WRo pulse sets the Ready flag
iii
\
after a Low·going edge of CLK, Indicating
(
>-
data ts available. Ready stays active until the
DATA
OUT
positive edge of the . t.robe line Is
recelv~d.
\
I
Indicating that data
WdS
tak.en by the perlph-
M·
era!. The positive edge of the strobe pulse
'iiD • Jiii •
~
• CiI5 • iOiiQ
generates an
00
If the Interrupt enable flip-
flop has been set arid If this device has the
FIguN 13. lINd
CycJ.
T.......
g
highest priority.
eLl(
_T
-----.....r----JI..----+----4........
OUT....T
-----.J''---t----..,f----+_-
READY
--------'
FIguN It•.
M9dot
0
Outpllt
TIaWlg
2006-0324,
0325, 0326
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