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Timing
(Continued)
Input Mod. (Model). When STROBE goes
Low, data is loaded into the selected port input
register (Figure 15). The next rising edge of
strobe activates INT, if Interrupt Enable is set
and this is the highest-priority requesting
device. The following falling edge of CLK
resets Ready to an inactive state, indicating
that the input register is full and cannot accept
any more data until the CPU completes a read.
When a read is complete, the positive edge of
RD sets Ready at the next Low-going transition
of CLK. At thiS time new data can be loaded
into the PIO.
CLK
RD'
- - - - - - - - - f J f - - - - - , .
·RO
=
RO· CE •
c/o·
IORQ
Figure 15. Mode I Inpul Timing
Bidirectional Mod. (Mod. 2). This is a com-
bination of Modes 0 and 1 using all four hand-
shake lines and the eight Port A I/O lines
(Figure 16). Port B must be set to the bit mode
and its inputs must be masked. The Port A
handshake lines are used for output control
and the Port B lines are used for input control.
If interrupts occur, Port A's vector will be used
during port output and Port B's will be used
during port input. Data is allowed out onto the
Port A bus only when ASTB is Low. The rising
edge of this strobe can be used to latch the
data into the peripheral.
CLK
ItQRTA,
--------:------C~~C>_----_<
DATA BUS
."0'1'
A,RDY
_ _ _ _ _ _ _-J
Figure 16. Mode 2 Bldlrecllonal Timing
2006·0327. 0328
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