ADC SUPER SIX S-100 Technical Manual page 111

Pin
Description
(Continued)
Internal
Structure
INT/PULSE. Interrupt Request
(0ulp'J!,
~r;'I'I'"
Low, open drain). This requests a CPU mter-
rupt. The CPU acknowledges the
intefr1~
by
pulling its IORQ output Low during an Ml
cycle. It is typically connected to the INT pin
of the CPU with a pullup resistor and tied to
all other INT pins in the system. This pin can
also be used to generate periodic pulses to an
external device. It can be used this way only
when the DMA is bus master (i.e" the CPU's
BUSREQ and BUSACK lines are both Low
and the CPU cannot see interrupts).
IORQ. Input/Output Request (bidirectional,
active Low, 3-state). As an input, this indicates
that the lower half of the address bus holds a
valid I/O port address for transfer of control or
status bytes from or to the CPU, respectively;
this DMA is the addressed port if its CE pin
and its WR or RD pins are simultaneously
active. As an output, after the DMA has taken
control of the system buses,
it
indicates that
the 8-bit or l6-bit address bus holds a valid
port address for another I/O device involved in
a DMA transfer of data. When IORQ and Ml
are both active simultaneously, an interrupt
acknowledge is indicated.
Ml. Machine Cycle One (input, active Low).
Indicates that the current CPU machine cycle
is an instruction fetch. It is used by the DMA
to decode the return-from-interrupt instruction
(RETI) (ED-4D) sent by the CPU. During two-
byte instruction fetches, Ml is active as each
The internal structure of the 2-80 DMA
includes driver and receiver circuitry for inter-
facing with an 8-bit system data bus, a 16-bit
system address bus, and system control lines
(Figure 6). In a 2-80 CPU environment, the
DMA can be tied directly to the analogous pins
on the CPU (Figure 7) with no additional buf-
fering, except for the CElWAIT line.
The DMA's internal data bus interfaces with
the system data bus and services all internal
logic and registers. Addresses generated from
this logic for Ports A and B (source and des-
tination) of the DMA's single transfer channel
are multiplexed onto the system address bus.
CONTROL\r
--.f.
')pcude
byte
IS
ie!ched. An ,nrerrupt ack-
nowledge
IS
mdicated when both MT and
fORD
are active.
MREQ.
Memory Request (output, active Low,
3-state). This indicates that the address bus
holds a valid address for a memory read or
write operation. After the DMA has taken con-
trol of the system buses, it indicates a DMA
transfer request from or to memory.
RD. Read (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU want,.
to read status bytes from the DMA's read
registers. As an output, after the DMA has
taken control of the system buses, it indicates a
DMA-controlled read from a memory or 1I0
port address.
ROY.
Ready (input, programmable active Low
or High). This is monitored by the DMA to
determine when a peripheral device associated
with a DMA port is ready for a read or write
operation. Depending on the mode of DMA
operation (Byte, Burst or Continuous), the RDY
line indirectly controls DMA activity by caus-
ing the BUSREQ line to go Low or High.
WH. Write (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU wants
to write control or command bytes to the DMA
write registers. As an output, after the DMA
has taken control of the system buses, it
indicates a DMA-controlled write to a memory
or 1I0 port address.
Specialized logic circuits in the DMA are
dedicated to the various functions of external
bus interfacing, internal bus control, byte
matching, byte counting, periodic pulse
generation, CPU interrupts, bus requests and
address generation. A set of twenty-one
writable control registers and seven madable
slatus registers provides the means by which
the CPU governs and monitors the activities of
these logic circuits. All registers are eight bits
wide, with double-byte information stored in
adjacent registers. The two address· counters
(two bytes each) for Ports A and B are buffered
by the two starting addresses.
anUM
ADDR•••
Bua
I'. BIT)
2032-0130
Figure 6. Block Diagram