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Pin
Description
Ao-
.A7. Port A Bus
(bidirectionaL 3-state).
This 8-bit bus transfers data, status, or control
information between Port A of the PIO and a
peripheral device.
A<J
is the least significant
bit of the Port A data bus.
.AHOY. Register A Ready (output, active
High). The meaning of this signal depends on
the mode of operation selected for Port A as
follows:
Output Mode. This signal goes active to indicate that the
Port A output register has been loaded and the peripheral
data bus is stable and ready for transfer to the peripheral
device.
Input Mode. This signal is active when the Port A input
register is empty and ready to accept data from the
peripheral device.
Bidirectional Mode. This signal is active when data is
available in the Port A output register for transfer to the
peripheral device. In this mode, data is not placed on the
Port A data bus, unless ASTB is active.
Control Mode. This signal is disabled and forced to a Low
state.
ASTB.
Port A Strobe Pulse From Peripheral
Device (input, active Low). The meaning of
this signal depends on the mode of operation
selected for Port A as follows:
Output Mode. The positive edge of this strobe is issued by
the peripheral to acknowledge the receipt of data made
available by the PIO.
Input Mode. The strobe is issued by the peripheral to load
data from the peripheral into the Port A input register.
Data is loaded into the PIO when this signal is active.
Bidirectional Mode. When this signal is active, data from
the Port A o~tPut register is gated onto the Port A bidirec·
tional data bus. The positive edge of the strobe acknowl·
edges the receipt of the data.
Control Mode. The strobe is inhibited internally.
80-1,.
Port B Bus (bidirectionaL 3-state). This
8-bit bus transfers data, status, or control
information between Port B and a peripheral
device. The Port B data bus can supply
1.5 rnA at 1.5 V to drive Darlington transistors.
Bo
is the least significant bit of the bus.
B/A. Port B Or A Select (input, High
=
B).
This pin defines which port is accessed during
a data transfer between the CPU and the PIO.
A Low on this pin selects Port A; a High
selects Port B. Often address bit
A<J
from the
CPU is used for this selection function.
BRDY. Register B Ready (output, active High).
This signal is similar to ARDY, except that in
the Port A bidirectional mode this signal is
High when the Port A input register is empty
and ready to accept data from the peripheral
device. .
BSTB.
Port B Strobe Pulse From Peripheral
Device (input, active Low). This signal is
similar to ASTB, except that in the Port A
bidirectional mode this signal strobes data
from the peripheral device into the Port A
input register.
cin.
Control Or Data Select (input,
High = C). This pin defines the type of data
transfer to be performed between the CPU and
the PIO. A High on this pin during a CPU
write to the PIO causes the Z-80 data bus to be
interpreted as a command for the port selected
by the
B/A
Select line. A Low on this pin
means that the Z-80 data bus is being used to
transfer data between the CPU and the PIO.
Often address bit Al from the CPU is used for
this function.
CEo Chip Enable (input, active Low). A Low
on this pin enables the PIO to accept com·
mand or data inputs from the CPU during a
write cycle or to transmit data to the CPU duro
ing a read cycle. This signat is generally
decoded from four 1/0 port numbers for Ports
A and B, data, and control.
ClK. System Clock (input). The Z-80 PIO uses
the standard single-phase Z·80 system clock.
Do-~.
Z-80 CPU Data Bus (bidirectional,
3-state). This bus is used to transfer all data
and commands between the Z-80 CPU and the
Z-80 PIO. Do is the least significant bit.
lEI. Interrupt Enable In (input, active High).
This signal is used to form a priority-interrupt
daisy chain when more than one interrupt-
driven device is being used. A High level on
this pin indicates that no other devices of
higher priority are being serviced by a CPU
interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). The lEO signal is the other signal
required to form a daisy chain priority scheme.
It is High only if IEI is High and the CPU is
not servicing an interrupt from this PIO. Thus
this signal blocks lower priority devices from
interrupting while a higher priority device is
being serviced by its CPU interrupt service
routine.
INT. Interrupt Request (output, open drain,
active Low). When INT is active the Z-80 PIa
is requesting an interrupt from the Z-80 CPU.
10RQ. Input/Output Request (input 'from Z·80
CPU, active Low). 10RQ is used in conjunc-
tion with
BiA:, ciiS,
CE, and RD to transfer
commands and data between the Z·80 CPU and
the Z-80 Pia. When CE, RD, and
I<:JRC::j
are
active, the port addressed by
B/A
transfers
data to the CPU (a read operation). Con-
versely, when
cr
and tORQ are active but RD
is not, the port addressed by BiAis written
into from the CPU with either data or control
information, as specified by
ciiS.
Also, if
IORQ and Ml are active simultaneously, the
CPU is acknowledging an interrupt; the inter-
rupting port automatically places its interrupt
vector on the CPU data bus if it is the highest
priority device requesting an interrupt.
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