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Functlonal
DetK:rlption
(Continued)
In all modes, once a byte of data is read into
the DMA, the operation on the byte will be
completed in an orderly fashion, regardless of
the state of other signals (including a port's
Ready line).
Due to the DMA's high-speed buffered
method of reading data, operations on one
byte are not completed until the next byte is
read In. This means that total transfer or
search block lengths must be two or more
bytes, and that block lengths programmed into
the DMA must be one byte less than the
desired block length (count is N-] where N is
the block length).
Commands and Statu. The 2-80 DMA has
several writable control registers and readable
status registers available to the CPU. Control
bytes can be written to the DMA whenever the
DMA is not controlling the system buses, but
the act of writing a control byte to the DMA
disables the DMA until it is again enabled by a
specific command. Status bytes can also be
read at any such time, but writing the Read
Status Byte command or the Initiate Read
Sequence command disables the DMA.
Control bytes to the DMA include those
which effect immediate command actions such
as enable, disable, reset, load starting-address
buffers, continue, clear counters, clear status
bits and the like. In addition, many mode-
setting control bytes can be written, including
mode and class of operation, port configura-
tion, starting addresses, block length, address
counting rule, match and match-mask byte,
interrupt conditions, interrupt vector, status-
affects-vector condition, pulse counting, auto
restart, Ready-line and Wait-line rules, and
read mask.
Readable status registers include a general
status byte reflecting Ready-line, end-of-block,
byte-match and interrupt conditions, as well as
2-byte registers for the current byte count,
Port A address and Port B address.
Variable Cycle. The 2-80 DMA has the
unique feature of programmable operation-
cycle length. This is valuable in tailoring the
DMA to the particular requirements of other
system components (fast or slow) and max-
Imizes the data-transfer rate. It also eliminates
exterriallogic for signal conditioning.
There are two aspects to the variable cycle
feature. First, the entire read and write cycles
(periods) associated with the source and
destination ports can be independently pro-
grammed as 2,3 or 4 I-cycles long (more if
Wait cycles are used), thereby increasing or
decreasing the speed with which all DMA
signals change (Figure 5).
Second, the four signals in each port
specifically associated with transfers of data
(I/O Request, Memory Request, Read, and
Write) can each have its active trailing edge
terminated one-half T-cycle early. This adds a
further dimension of flexibility and speed,
allowing such things as shorter-than-normal
Read or Write signals that go inactive before
data starts to change.
Address Generation. Two I6-bit addresses are
generated by the 2-80 DMA for every transfer
operation, one address for the source port and
another for the destination port. Each address
can be either variable or fixed. Variable
addresses can increment or decrement from
the programmed starting address. The fixed-
address capability eliminates the need for
separate enabling wires to VO ports.
Port addresses are multiplexed onto the
system address bus, depending on whether the
DMA is reading the source port or writing to
the destination port. Two readable address
counters (2 bytes each) keep the current
address of each port.
Auto Restart. The starting addresses of either
port can be reloaded automatically at the end
of a block. This option is selected by the Auto
Restart control bit. The byte counter is cleared
when the addresses are reloaded.
The Auto Restart feature relieves the CPU of
software overhead for repetitive operations
such as CRT refresh and many others. More-
over, when the CPU has access to the buses
during byte-at-a-time or burst transfers, dif-
ferent starting addresses can be written into
buffer registers during transfers, causing the
Auto Restart to begin at a new location.
Interrupts. The 2-80 DMA can be programmed
to interrupt the CPU on three conditions;
• Interrupt on Ready (before requesting bus)
• Interrupt on Match
• Interrupt on End of Block
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