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Active State
Timing
(DMA as Bus
Controller)
(Continued)
Bus Release Byte-at-a-Tlme. In Byte-at-a-
Time mode, BUSREQ is
brou~ ~
QIl
the
rising edge of CLK prior to
~
...-e..ach
read cycle (search-only) or write cycle
(transfer and transfer/search) as illustrated in
Figure 16. This is done regardless of the state
of RDY. There is no possibility of confusion
when a 2-80 CPU is used since the CPU
cannot begin an operation until the "following
T-cycle. Most other CPUs are not bothered by
this either, although note should be taken of it.
The next bus request for the next byte will
come after both BUSREQ and BAI have
returned High.
Bus Release at End of Block. In Burst and
Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Figure 17). The last
byte in the block is transferred even if RDY
goes inactive before completion of the last byte
transfer.
Bus Release on Not Ready. In Burst mode,
when RDY goes inactive it causes BUSREQ to
go High on the next rising edge of CLK after
the completion of its current byte operation
(Figure 18). The action on BUSREQ is thus
somewhat delayed from action on the RDY
line. TheDMA always completes its current
byte operation in an orderly fashion before
releasing the b_. ; :u, " =s"""
= =
By contrast, BUSREQ is not released in
Continuous mode when RDY goes inactive.
... J"lJ)Lf1..JLJL..n..Il.
ovou.
-.r+.,...----------
I
iii
I
r---------
_ _ _ _..... 1. I
I'~
f*A AalVE ~ DMA INACTIVE
Flgur.o i6. BIUI R.I...... (Dyt.-at-a-Tlm. Mod.)
...
IIIilACnvE
-
----.....,,.---1-'
Flgur.o i8. DIUI R.I_ Wh.n Nol Ready
(Dunt Mod.)
Instead, the DMA idles after completing the
current byte operation, awaiting an active RDY
again.
BUll Release on Match. If the DMA is pro-
grammed to stop on match in Burst or Con-
tinuous modes, a match causes BUSREQ to go
inactive on the .next DMA operation, i.e., at
the end of the next read in a search or at the
end of the following write in a transfer (Figure
19). Due to the pipelining scheme, matches
are determined while the next DMA read or
write is being performed.
The RDY line can go inactive after the
matching operation begins without affecting
this bus-release timing.
Interrupts. Timings for interrupt acknowledge
and return from interrupt are the same as tim-
ings for these in other 2-80 peripherals. Refer
to 2ilog Application Note 03-0041-01 (The Z-80
Family Program Interrupt Structure).
Interrupt on RDY (interrupt before request-
ing bus) does not directly affect the BUSREQ
line. Instead, the interrupt service routine
must handle this by issuing the following
commands to WR6:
1. Enable after Return From Interrupt (RETIl
Command - Hex B7
2. Enable DMA - Hex 87
3. An RET! instruction that resets the
Interrupt Under Service latch in the
2-80 DMA.
ACTIVE
.0.
INACTIVE
iui".Q - - - - -......
r;-----t'
Flgurei? 8IUI Rel_ at
Eocl
of I8lodt
(Bunt
_d ConUnuolU Mod..)
Figur. 19. DUll Rel_ _ Match
(Dural _d ConilnuoUII Mod..)
2032·0140, 0141. 0142, 0143
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