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SECTION II
OPERATION
This section describes the operation of all SUPER SIX components.
2.1
FLOPPY DISK CONTROLLER
The floppy disk controller can access up to four 8:'inch or four 5.25-inch disk drives or any
combination of the two. The controller can read and write
IBl\\
3740 single density format
and double density 1024 sector-SIze formats.
Data transfer is performed via Direct
Memory Access (DMA). Due to the simultanious operation capability of the SUPER SIX
the format compatibility problems with 5.25-inch disks have Deen eliminated. The floppy
disk controller used is the W
D27~3.
The WD2793 has on-chip PLL data separators and
on-chip write pre-compensation logic. Adjustments for PLL are factory set dno write
pre-compensation has been provided with the SUPER SIX. 50 Pin and 34 pin connectors
are available for 8-inch and 5.25-inch disk drives respectively.
NOTE:
Customer adjustment of trim pots
may result in cancellation of warranty.
2.2
THE l28K DYNAMIC RAM
The 128K RAM array can be switched ON and OFF in 16K increments, (O-loK, 16K-32K,
32K-48K, 48K-64K for both banks) under software control. This feature allows the CPU
to access bank switchable external memory on the 5-100 bus. The memury tlas an access
time of 150ns. A Refresh operation is performed during 280 M I cycles and during WAlI
and RESET states.
The memory can be accessed by floppy dISk via DI\iIA, serial and
paralielljO, or another DMA device un the S-IOO bus.
*NOTE:
Any external DMA deVIce that is
using
continous
mode
DMA
cycles
must
transfer data at an average rate of 15ms per
byte or faster when holding the DMA request
line for more than 1.5ms.
The RAM row
address is the low order address; therefore
the entire RAM array is refreshed by DMA
device every
i
28 contiguous memory cycles.
Under CPM 2.2 or CPM 3.0 the additional 64K can be used as a diSk buffer. The SUPER
SIX is ideal when operating in the bank mode under CP jM 3.0, as 128K l{AM is required.
-4-
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