Local Bus - Alpha Data ADM-XRC-II User Manual

5.6.

Local Bus

The local bus of the ADM-XRC-II uses the PCI9656 to provide a non-
multiplexed address and data capability with synchronous speeds of up to
66MHz, independent of PCI operation. Whilst the local bus is capable of
achieving near PCI performance, it is much simpler to interface with than PCI.
The ADM-XRC-II routes most of the local bus signals to the FPGA and
devotes an entire address space to the FPGA.
The signals provided are :-
Signal Active
LA[31:2] high
LBE[3:0} low
LD[31:0] high
LWRITE high
LBLASTL low
LADSL low
LBTERML low
LREADYIL low
LDREQL[1:0] low
LDACKL[1:0] low
LEOTL[1:0] low
LINTIL low
FHOLD high
FHOLDA high
LRESETOL low
LCLKA high
The local bus provides 8Mbytes of address space for the FPGA to use for
whatever purpose is desired by the application. LA[23]=0 should be used to
determine when the FPGA is being accessed.
Example Verilog code demonstrates how to interface to the local bus and
provide access to the SSRAM's for test purposes. User applications can
define how the address space allocated to the FPGA is mapped to the local
bus and may or may not provide access to the SRAM memory.
Direction Purpose
IN Address
IN Address/byte enables
BIDIR Data Bus
IN Write cycle when true, read when false
IN End of burst
IN Address / data start
OUT/TRI Burst terminate
OUT/TRI Accepts/completes data transfer
OUT Request DMA transfer
IN DMA transfer acknowledge
OUT Terminate current DMA transfer
OUT Interrupt (via CPLD)
OUT Reserved for future use
IN Reserved for future use
IN Reset from PLX and PCI
IN Local bus clock (VCLK from ICS9161)
ADM-XRC-II User Manual
ADM-XRC-II User Manual
Version 1.5
Page 12