Pci Bus Interface - Alpha Data ADM-XRC-II User Manual

4.

PCI Bus Interface

The PCI bus is implemented in a PLX PCI9656 and is configured with settings
as described later in this document to simplify the integration of user
applications in the FPGA.
The PCI configuration space of the ADM-XRC-II is shown below.
Config.
Offset
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
The PCI9656 uses the first two Bar's to provide access to its internal registers
both via memory accesses and I/O accesses. Either BAR may be used by the
host.
BAR 2 provides access to a 4Mbyte space for use by the FPGA and must be
accessed only when a valid FPGA configuration is loaded that can respond
correctly to local bus access.
BAR 3 provides access to the local control registers and the flash memory.
31 24 23 16
Device ID
(0042)
(9656)
Status
Class Code
BIST HeaderType
PCI BAR0
(PLX Internal Registers/Memory)
PCI BAR1
(PLX Internal Registers/IO)
PCI BAR2
(Local Bus FPGA)
PCI BAR3
(Local Bus Control/Flash/SelectMap)
PCI BAR4
(Not used)
PCI BAR5
(Not used)
Card Bus CIS Pointer(Not used)
Subsystem ID
PCI Base Address for Local Expansion ROM
Reserved
Reserved
Max Lat Min Gnt
ADM-XRC-II User Manual
15 8 7
Vendor ID
(4144)
(10B5)
Command
RevisionID
Lat. Timer Cache Line
Subsystem Vendor ID
Int. Pin Int. Line
ADM-XRC-II User Manual
0
Version 1.5
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