Output Clocks - Alpha Data ADM-XRC-II User Manual

ADM-XRC-II User Manual
VCLK is input to the FPGA on GCK1 (pin AF18) and can be used for any
purpose within the FPGA.
5.5.

Output Clocks

The FPGA is responsible for providing clocks to the SRAM's and also for
aligning its internal global clock with the local bus clock. To do this requires
the use of Virtex DCM's that are specifically designed for the purpose of
minimising skew between external and internal clock domains.
The SRAM's are split into two banks of three – each bank of three has its
own FPGA clock output and feedback pin to allow deskewing within the
FPGA. Further details of SRAM clocking are provided in section 5.8.
ADM-XRC-II User Manual
Version 1.5
Page 11