Local Configuration Registers; Mode/Arbitration Register; Big/Little Endian Descriptor Register; Region 0 Descriptor - Alpha Data ADM-XRC-II User Manual

9.2.

Local Configuration Registers

The PCI9656 Local Bus provides two main address spaces through which
accesses to local bus resources can be made. As described earlier, S0 is a
4Mbyte space that is 32 bits wide, allocated to the FPGA. S1 is also a 4Mbyte
space and is allocated to the flash prom and control registers. The Local
Configuration registers are shown below in summary with more detailed
descriptions following them.

9.2.1. Mode/Arbitration Register

The Mode/Arbitration Register is usually set by the EEPROM initialisation and
left unaltered after boot.
The PCI Rev 2.1 Mode pin sets the behaviour of the PCI9656 to conform to
PCI revision 2.1 with regard to posted transactions.
The PCI Read No Write Mode bit is set to cause PCI writes to the PCI9656 to
retry whilst a posted read is pending. This is a known workaround in REV 3
silicon.

9.2.2. Big/Little Endian Descriptor Register

This register can be used to force big endian mode for various transfers. The
ADM-XRC-II does not perform any endian conversions by default.

9.2.3. Region 0 Descriptor

The Region 0 Descriptor describes the attributes of Local Bus Space 0. It can
be seen that 32 bit local bus width is selected and that ready must be
generated by the target space. In this case, Space 0 is allocated to the FPGA
so all accesses to Space 0 must be acknowledged by the FPGA.
The BTERM bit is set which means that bursts of greater the four LWORD's
are permitted. This also means that the FPGA can break a burst transfer into
smaller lengths by asserting BTERM. No wait states are generated by the
PCI9656 for Space 0 - all wait states are determined by the FPGA.
The Expansion ROM Space is not currently used in the ADM-XRC-II.
The Extra Long Load from Serial EEPROM bit is set to indicate that a long
load did occur during the EEPROM read cycle. The length of the EEPROM
load is determined by the contents of the EEPROM.
Notes.
1. The bus width of memory space 0 is set to 32 bits by default. As this region
is totally under control of the FPGA, it may be changed. It is the
responsibility of the FPGA designer to take this into account.
2. The Extra Long Load from Serial EEPROM bit indicates that the extended
EEPROM load was performed. This is required to set up Space 1 and
some other registers.
3. Expansion ROM Space is not implemented in the ADM-XRC-II and should
not be altered.
ADM-XRC-II User Manual
ADM-XRC-II User Manual
Version 1.5
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