Local Bus; Table 1 Local Bus Interface Signal List; Figure 2 Local Bus Interface - Alpha Data ADM-XRC-5T2-ADV User Manual

Pci mezzanine card
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4.1.

Local Bus

The ADM-XRC-5T2-ADV implements a multi-master local bus between the bridge and the
target FPGA using a 32- or 64-bit multiplexed address and data path. The bridge design is
asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to
suit the requirements of the user design.
Signal
lad[63:0]
lbe_l[7:0]
lads_l
lblast_l
lbterm_l
lready_l
lwrite
ldreq_l[3:0]
ldack_l[3:0]
fhold
fholda
lreset_l
lclk
ADM-XRC-5T2-ADV User Manual
Version 1.0
Page 4

Figure 2 Local Bus Interface

Type
Purpose
bidir
Address and data bus.
bidir
Byte qualifiers
bidir
Indicates address phase
bidir
Indicates last word
bidir
Indicates ready and requests new address phase
bidir
Indicates that target accepts or presents new data
bidir
Indicates a write transfer from master
unidir
DMA request from target to bridge
unidir
DMA acknowledge from bridge to target
unidir
Target bus request
unidir
Bridge bus acknowledge
unidir
Reset to target
unidir
Clock to synchronise bridge and target

Table 1 Local Bus Interface Signal List

ADM-XRC-5T2-ADV User Manual

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