Icon Registers; Pstat Register - Alpha Data ADM-XRC-II User Manual

5.2.3. ICON Registers

The ICON registers consist of a mask register and an interrupt status register.
The mask register can be set or cleared by writing to IMSET or IMCLR with a
bit mask. The XRC only supports one interrupt from the local bus and is
masked, set or cleared using bit 0. On reset the mask bits are set disabling
local bus interrupts.
7 6
IMSET MBZ MBZ
IMCLR MBZ MBZ
IMSTAT RAX RAX
The ICON register contains the status of the interrupt from the FPGA. This bit
can be read independently of the state of the FINTM mask bit.
The method used to clear FINT in the ISTAT register depends on the interrupt
mode selected by IMODE (MODE [0]).
• With edge-triggered interrupts, writing the FINT bit in ICON clears the
corresponding bit in ISTAT.
• For level sensitive interrupts, FINT can only be cleared by removing the
interrupting source in the FPGA.
7 6
ICON MBZ MBZ
ISTAT RAX RAX

5.2.4. PSTAT Register

The PSTAT register presents information about the power supply to the Virtex
device. The XRC generates power for the FPGA core from 5V, using a switch
mode supply circuit that outputs two signals to indicate over-temperature and
accuracy.
7 6
PSTAT RAX RAX
PGOOD
PTEMP
5 4
MBZ MBZ
MBZ MBZ
RAX RAX
5 4
MBZ MBZ
RAX RAX
5 4
RAX RAX
0 => PSU is out of range
1 => PSU is within +/- 10%
0 => PSU has shutdown (thermal detect)
1 => PSU is within operating range
ADM-XRC-II User Manual
3 2 1
MBZ MBZ MBZ
MBZ MBZ MBZ
RAX RAX RAX
3 2 1
MBZ MBZ MBZ
RAX RAX RAX
3 2 1
RAX RAX PTEMP
ADM-XRC-II User Manual
0
FINTM W
FINTM W
FINTM R
0
FINT W
FINT R
0
PGOOD R
Version 1.5
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